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Xiaohan Yang is originally from China. She joined Oxford Brookes as a research student in September 2015 and the title of her thesis is ‘Design Analysis and Tests of Reliable Memristor Based Logic Architectures’.
I first heard about Oxford Brookes University through one of the visiting research fellows from the University of Bristol.
There is a lot of impressive work being done by the Advanced Reliable Computer Systems Group (ARCoS) and this attracted me to Oxford Brookes to conduct my research.
Before joining Brookes, I was working as a hardware engineer for CETC 28th (China Electronics Technology Group Corporation No. 28 Research Institute).
My supervisor, Dr Abusaleh Jabir, provided excellent support when I first joined Brookes and helped me to settle in quickly and access the Cadence (one of the most professional EDA tools).
Introduction of the memristor and memristive based systems
Metal Oxide Semiconductor (MOS) transistor-based chips are currently being limited by scaling difficulties and parasitic capacitance. Therefore, chip manufactures are beginning to invest huge resource in order to explore alternative technologies for the evolution of computing devices. A memristor (short for “memory –resistor”), a two terminal nano-scale electronic device, is a highly promising technology as an alternative. The basic concept of the memristor was theorized by Leon Chua in 1971, which indicates the missing link between the charge (q) and flux (φ). Hence, the memristor operates in following ways: the resistance of the memristor is not a constant but depends on the history of the current that had previously followed through the device. It retains its previous resistance value after power has been removed, thereby remaining non-volatile. Since Hewlett-Packard fabricated the first physical memristive device based on titanium dioxide (TiO2) in 2008 -, there has been increasing interest in different aspects of memristor applications such as high density memory design, neuromorphic systems, secure and crypto systems and logic design. The memristor can be interfacing with the existing CMOS technology, owing to the fact that they both share the similar fabrication properties. Additionally, it also can be scaled very small geometry and can be fabricated in layer upon layer, thereby providing a 3D compact architecture for hybrid memristor –CMOS chips.
Proposed memristor based logic architecture
Most of the techniques for designing logic circuits with memristors require multiple sequential steps and complex control logic to realise even the simplest logic function. While there are some existing techniques which operate on single cycle operation fail to work with realistic resistance value and require more power. In MPhil state, firstly we investigate the different behaviour models of the memristor and by modifying and improving those models we generalise an asymmetric hysteresis I-V characteristic for logic design particularly. Then, we propose a single cycle purely memristive logic XOR architecture, consisting of only 4 memristors. We seamlessly integrate this architecture with only one transistor, thereby resulting a hybrid 1T-4M architecture with dual XOR/AND and XNOR/OR functionality. (We have a patent published on this part of work. Further details may be found from my supervisor Dr Abusaleh M. Jabir email@example.com and the RBDO.) Meanwhile, we also propose memristive MIN-MAX functionality by realising that memristor have inherent properties for the multiple valued logic. Recent technological advances are seeing memristors operating at much higher frequencies. Hence, we explore the effects of frequencies on the physical parameters of memristor; thereby propose a reliable high frequency design technique based on our 1T-4M architectures. To this end, with help of memristive full adder design and memristive bit parallel multiplier over GF(24) design, we show that our proposed memristive logic architecture require considerably low power and low overhead while maintaining the reliable performance at low as well as high frequencies.
Parasitic effects on memristive logic architecture
Since the first physical memristive device was fabricated at HP lab in 2008, a number of memristor models have been proposed rapidly with their own attributes (e.g. symmetricity and operating frequency). However, none of these models are take the parasitic effects into consideration. To meet the reality properly, the latest released generic memristor model consists of the memristor basic model in parallel with a parasitic capacitor and a current source. Then, they connect in series with a parasitic inductor and voltage source. The parasitic capacitor and parasitic inductor joined here are specifically to emulate those physical effects which might cause pinched point of the I-V hysteresis loop shift from the origin or even disappeared after the circuit operating above the certain frequency. To investigate parasitic effects on proposed memristive XOR gate, we input a unit step function to a single generic memristor model. Owing to the effects of the parasitic elements which form a second-order circuit, hence, the output demonstrates the decaying oscillation. We applied this generic model to our XOR circuit. The experimental results shows that most of the decaying oscillations generated by the parasitic components have been cancelled effectivity due to the bridge connection. These results have been published in our paper. The paper also observed that parasitic components can generate more propagation delay and increase the degree of the randomness for the processing variation. These characteristics lead to a starting point on the memristive arbiter physical unclonable function.
Physical Unclonability in Memristive Hybrid Systems
Physical unclonability based memristive hybrid system is inspired by the previous work and experimental results which I described above. In the present era, electronic devices are prevalent in our daily lives which lead to highly demand on implementing a reliable cryptographic system. Conventional crypto-system relied on mathematic or algorithm is basically keeping the binary keys secretly. However, most of these technologies require extra chip area, high power consumption and high manufacturing costs. Unfortunately, those keys can also be exposed easily by cryptographic attack techniques such as modelling attacks, side-channel attacks and Brute-Force attacks. To create a lightweight, low power and low cost system with maintaining the high security level is a challenge. Physical Unclonable Function (PUF) was just invented decade ago. It has been applied for the key generation and challenge-response authentication. Comparing with the conventional cryptographic system, this emerging technology uses the manufacturing variation of the physical device as the source of the security primitive especially when the device scaling down to the nano-meter. For example, uncontrollable random variation of the doping concentration and undesirable difference in physical dimension (e.g. channel length, width etc.) lead to the device being extremely difficult to be re-fabricated. Memristor as one of the most well-known emerging nano-scale electronic devices realises a highly random variation owing to internal parasitic elements which has been shown on paper and state clearly in the previous section. This parasitic inherent property induces the memristor based security primitives much stronger than conventional metal oxide semiconductor based security primitives. Based on our hybrid memristive XOR architecture, we built up a 16-bits delay based arbiter PUF which shows acceptable uniqueness, uniformity and reliability. This is still ongoing research. More analysis and optimisation need to be done.
Fault Models for Memristive Logic Architecture & Novel Technique to Mitigate Sneak-Path
To achieve high-quality of memristor based circuit, we need to explore test factors and build fault models to identify and diagnose faults. Then apply the test with stress such as high voltage and frequency to detect the potential defects of memristors to achieve high reliability. Some faults that have been identified with the memristor include Stuck-At Fault which means the state of output circuit stuck in state one or state zero; and Undefined State Fault which means the output of the circuit is neither one nor zero.
Another major challenge in the memristive logic architecture is sneak-path problem, which in turn leads to erroneous results and excessive power consumption. So far, none of the proposed techniques have been able to eliminate sneak-path without any drawbacks.
The overall aim for this stage is to design large reliable memristive logic system which could lead to high frequency, low power and low area chip design.
The scholarship has helped me to save money from tuition fees and buy some research related material (i.e. paid Journals). I am able to manage my expenses properly, which has enabled me to concentrate more on my study.
I would like to continue my research within this field.