Dr Steve Barker
PhD, MBA, Dip(M), PCTHE, FHEA
Senior Lecturer in Electronic Engineering
School of Engineering, Computing and Mathematics

Role
As well as teaching Electronics, Control Systems, and Sensors and Data Logging I am also heavily involved in research. My research interest encompass (amongst other things) Biomedical Electronics, Autonomous Vehicle Control Systems and Radio Frequency Circuits.
I also supervise Undergraduate, Postgraduate and Research Degree student projects.
Teaching and supervision
Courses
Modules taught
I am the Module Leader for:
- Electronic Systems
- Control Technology
- Sensors and Data Logging
And I also teach Management on another module.
Supervision
I have supervised a number of PhD and Masters by Research students through to completion. I am always interested to hear from potential research students about their project ideas.
Research
My research interest encompass (amongst other things) Biomedical Electronics, Autonomous Vehicle Control Systems and Radio Frequency Circuits. Current projects include Artificial Intelligence based techniques for artefact minimisation in biomedical systems, driver distraction technology, Electrical Impedance Tomography mammogram design, and image enhancement for MRI systems.
Groups
Publications
Journal articles
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Borislav Dimitrov , Khaled Hayatleh , Steve Barker and Gordana Collier, 'Design, Analysis and Experimental Verification of the
Self-Resonant Inverter for Induction Heating Crucible Melting Furnace Based on IGBTs Connected in Parallel'
Electricity 2 (4) (2021) pp.423-438
ISSN: 2673-4826 eISSN: 2673-4826AbstractPublished here Open Access on RADARThe object of this research was a self-resonated inverter, based on paralleled Insulated-Gate Bipolar Transistors (IGBTs), for high-frequency induction heating equipment, operating in a wide range of output powers, applicable for research and industrial purposes. For the nominal installed capacity for these types of invertors to be improved, the presented inverter with a modified circuit comprising IGBT transistors connected in parallel was explored. The suggested topology required several engineering problems to be solved: minimisation of the current mismatch amongst the paralleled transistors; a precise analysis of the dynamic and static transistors’ parameters; determination of the derating and mismatch factors necessary for a reliable design; experimental verification confirming the applicability of the suggested topology in the investigated inverter. This paper presents the design and analysis of IGBT transistors based on datasheet parameters and mathematical apparatus application. The expected current mismatch and the necessary derating factor, based on the expected mismatch in transistor parameters in a production lot, were determined. The suggested design was experimentally tested and investigated using a self-resonant inverter model in a melting crucible induction laboratory furnace.
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Nagulapalli R, Yassine N, Barker S, Georgiou P, Hayatleh K, 'A 261mV Bandgap reference based on Beta Multiplier with 64ppm'
International Journal of Electronics Letters 10 (4) (2021) pp.403-413
ISSN: 2168-1724 eISSN: 2168-1732AbstractPublished here Open Access on RADARIn this paper, a low voltage bandgap reference circuit has been proposed. The introduction of a modified beta multiplier bias circuit decreased the mismatch caused by the PMOS transistors opamp contribution. By shifting the fixed resistors to the NMOSs drain side, the beta multiplier bias was able to minimise threshold mismatch between the two NMOS transistors. A 200-point MC simulation showed 0.9mV standard deviation, with a 0.34% accuracy. The simulated temperature coefficient was 64ppm/0C. The proposed circuit consumed 5.04µW of power from a 0.45V power supply voltage. A prototype was implemented in 65nm CMOS technology occupying a 2888µm2 silicon area, with the nominal value of the reference at 261mV.
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Borislav Dimitrov *, Khaled Hayatleh, Steve Barker, Gordana Collier, Suleiman Sharkh, Andrew Cruden, 'A Buck-Boost Transformerless DC-DC Converter Based on IGBT Modules for Fast Charge of Electric Vehicles'
Electronics 9 (3) (2020)
ISSN: 2079-9292AbstractPublished here Open Access on RADARA transformer-less Buck-Boost DC-DC converter in usage for the fast-charge of electric vehicles, based on powerful high-voltage IGBT (Isolated Gate Bipolar Transistor) modules is analyzed, designed and experimentally verified. The main advantages of this topology are: simple structure on the converter’s power stage; a wide range of the output voltage, capable to support nowadays vehicles on-board battery packs; efficiency and power density accepted to be high enough for such class of hard-switched converters. A precise estimation of the loss, dissipated in the converter’s basic modes of operation – Buck, Boost, and Buck-Boost is presented. The analysis shows an approach of loss minimization, based on switching frequency reduction during the Buck-Boost operation mode. Such a technique guarantees stable thermal characteristics during the entire operation, i.e. battery charge cycle. As the Buck-Boost mode takes place when Buck and Boost modes cannot support the output voltage, operating as a combination of them, it can be considered as critically dependent on the characteristics of the semiconductors. With this, the necessary duty cycle and voltage range, determined with respect to the input-output voltages and power losses, require additional study to be conducted. Additionally, the tolerance of the applied switching frequencies for the most versatile silicon-based powerful IGBT modules is analyzed and experimentally verified. Finally, several important characteristics, such as transients during switch-on and switch-off, IGBTs voltage tails, critical duty cycles, etc., are depicted experimentally with oscillograms, obtained by an experimental model.
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Nagulapalli R, Hayatleh K, Barker S, 'A positive feedback-based op-amp gain enhancement technique for high precision applications'
Journal of Circuits, Systems, and Computers 29 (14) (2020)
ISSN: 0218-1266 eISSN: 1793-6454AbstractPublished here Open Access on RADARA power-efficient, voltage gain enhancement technique for op-amps has been described. The proposed technique is robust against Process, Voltage, and Temperature (PVT) variations. It exploits a positive feedback-based gain enhancement technique without any latch-up issue, as opposed to previously proposed conductance cancellation techniques. In the proposed technique, four additional transconductance-stages (gm stages) are used to boost the gain of the main gm stage. The additional gm stages do not significantly increase the power dissipation. A prototype was designed in 65nm CMOS technology. It results in 81dB voltage gain, which is 21dB higher than the existing gainboosting technique. The proposed opamp works with as low a power supply as 0.8V, without compromising the performance, whereas the traditional gain-enhancement techniques start losing
gain below a 1.1V supply. The circuit draws a total static current of 295μA and occupies 5000μm2 of silicon area. -
Nagulapalli R, Hayatleh K, Barker S, 'A VGA Linearity improvement technique for ECG analog front-end in 65nm CMOS'
Journal of Circuits, Systems, and Computers 29 (7) (2019)
ISSN: 0218-1266 eISSN: 1793-6454AbstractPublished here Open Access on RADARThis paper presents a 65nm CMOS low-power, highly linear variable gain amplifier (VGA) suitable for biomedical applications. Typical biological signal amplitudes are in the 0.5-100mV range, and therefore require circuits with a wide dynamic range. Existing VGA architectures mostly exhibit a poor linearity, due to very low local feedback loopgain. A technique to increase the loop-gain has been explored by adding additional feedback to the tail current source of the input differential pair. Stability analysis of the proposed technique was undertaken with pole-zero analysis. A prototype of Analog Front End (AFE) has been designed to provide 25-50dB gain, and post-layout simulations showed a 15dB reduction in the harmonic distortion for 20mV pk-pk input signal compared to the conventional architecture. The circuit occupies 3,108μm2 silicon area and consumes 0.43μA from a 1.2V power supply.
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R. Nagulapalli, K. Hayatleh, S. Barker, A. A. Tammam, F. J. Lidgey and N. Yassine, 'A High Sensitivity and Low Power Circuit for the Measurement of Abnormal Blood Cell Levels'
Journal of Circuits, Systems, and Computers 29 (4) (2019)
ISSN: 0218-1266 eISSN: 1793-6454AbstractPublished here Open Access on RADARThis paper describes a technique to detect blood cell levels based on the time-period modulation of a relaxation oscillator loaded with an Inter Digitated Capacitor (IDC). A digital readout circuit has been proposed to measure the time-period difference between the two oscillators loaded with samples of healthy and (potentially) unhealthy blood. A prototype circuit was designed in 65nm CMOS technology and post-layout simulations shows 15.25aF sensitivity. The total circuit occupies 2184µm2 silicon area and consumes 216µA from a 1V power supply.
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R. Nagulapalli, K. Hayatleh, S. Barker, B. Yassine, S. Zourob, S. Raparthy, N. Yassine, 'A Start-up Assisted Fully Differential Folded Cascode Opamp'
Journal of Circuits, Systems, and Computers 28 (10) (2018)
ISSN: 0218-1266 eISSN: 1793-6454AbstractPublished here Open Access on RADARThis paper explains the hidden positive feedback in the two-stage fully differential amplifier through external feedback resistors, and possible DC latch-up during the amplifier start-up. The biasing current selection among the cascode branches have been explained intuitively, With reference to previous literature. To avoid the latch-up problem irrespective of the transistor bias currents a novel, hysteresis based start-up circuit is proposed. An 87dB, 250MHz unity gain bandwidth amplifier has been developed in 65nm CMOS Technology and post-layout simulations demonstrate no start-up failures out of 1000 Monte-Carlo (6-Sigma) simulations. The circuit draws 126uA from a 1.2V supply and occupies the 2184um2 area.
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R. Nagulapalli, K. Hayatleh, S. Barker, A.A. Tammam, N. Yassine, B. Yassine, M. Ben-Esmael., 'A Low Noise Amplifier Suitable for Biomedical Recording Analog Front-End in 65nm CMOS Technology'
Journal of Circuits, Systems, and Computers 28 (8) (2018)
ISSN: 0218-1266 eISSN: 1793-6454AbstractThis paper presents a fully integrated Front-end, low noise amplifier, dedicated to the processing of various types of bio-medical signals, such as Electrocardiogram (ECG), Electroencephalography (EEG), Axon Action Potential (AAP). A novel noise reduction technique, for an operational transconductance amplifier (OTA), has been proposed. This adds a current steering branch parallel to the differential pair, with a view to reducing the noise contribution by the cascode current sources. Hence, this reduces the overall input referred noise of the Low Noise Amplifier (LNA), without adding any additional power. The proposed technique implemented in 65nm CMOS technology achieves 30dB closed loop voltage gain, 0.05Hz lower cut-off frequency and 100MHz 3-dB bandwidth. It operates at 1.2V power supply and draws 1µA static current. The prototype described in this paper occupies 3300µm2silicon area.Published here Open Access on RADAR -
R. Nagulapalli, K. Hayatleh, S. Barker, A.A. Tammam, P. Georgiou* & F. J. Lidgey, 'A 0.55V Bandgap reference with a 59ppm/0c Temperature coefficient'
Journal of Circuits, Systems, and Computers 28 (7) (2018)
ISSN: 0218-1266 eISSN: 1793-6454AbstractThis paper presents a novel low power, low voltage CMOS bandgap reference (BGR) that overcomes the problems with existing BJT-based reference circuits, by using a MOS transistor operating in subthreshold region. A proportional to absolute temperature (PTAT) voltage is generated by exploiting the self-bias cascode branch, while a Complementary to Absolute Temperature (CTAT) voltage is generated by using the threshold voltage of the transistor. The proposed circuit is implemented in 65nm CMOS technology. Post-layout simulation results show that the proposed circuit works with a supply voltage of 0.55V, and generates a 286mV reference voltage with a temperature coefficient of 59ppm/°C. The circuit takes 413nA current from 0.55V supply and occupies 0.00986mm2 of active area .Published here Open Access on RADAR -
K Hayatleh, S Zourob, R Nagulapalli,S Barker, N Yassine, P Georgiou*, F J Lidgey, 'A High Performance Skin Impedance Measurement Circuit for Biomedical Applications'
Journal of Circuits, Systems, and Computers 28 (7) (2018)
ISSN: 0218-1266 eISSN: 1793-6454AbstractThis paper describes a high-performance impedance measurement circuit for the application of skin impedance measurement in the early detection of skin cancer. A CMRR improvement technique has been adopted for OTAs to reduce the impact of high frequency common mode interference. A modified 3-OTA IA has been proposed to help with the impedance measurement. Such systems offer a quick, non-invasive and painless procedure, thus having considerable advantages over the currently used approach, which is based upon the testing of a biopsy sample. The sensor has been implemented in 65nm CMOS technology and post layout simulations confirms the theoretical claims we made and sensor exhibits sensitivity. Circuit consumes 45uW from 1.5V power supply. The circuit occupies 0.01954mm2 silicon area.Published here Open Access on RADAR -
R. Nagulapalli, K. Hayatleh, S. Barker, P. Georgiou & F. J. Lidgey, 'A High Value, Linear and Tunable CMOS Pseudo Resistor for Bio-medical Applications'
Journal of Circuits, Systems, and Computers 28 (6) (2018)
ISSN: 0218-1266 eISSN: 1793-6454AbstractA sub-threshold MOS based pseudo resistor featuring a very high value and ultra-low distortion is proposed. A band-pass neural amplifier with a very low high-pass cutoff frequency is designed, to demonstrate the linearity of the proposed resistor. A BJT less CTAT current generator has been introduced to minimize the temperature drift of the resistor and make tuning easier. The stand-alone resistor has achieved 0.5% better linearity and a 12% improved temperature coefficient over the existing architectures. A neural amplifier has been designed with the proposed resistor as a feedback element. It demonstrated 31dB mid-band gain and a lowpass cutoff frequency of 0.85Hz. The circuit operates from a 1V supply and draws 950nA current at room temperature.Published here Open Access on RADAR -
R. Nagulapalli, K. Hayatleh, S. Barker, S. Zourob, N. Yassine, S. Raparthy and A. A. Tammam, 'A novel high CMRR Trans-Impedance Instrumentation Amplifier for biomedical applications'
Analog Integrated Circuits and Signal Processing 98 (2018) pp.233-241
ISSN: 0925-1030 eISSN: 1573-1979AbstractA compact high gain current mode instrumentation amplifier (IA) has been proposed for biomedical imaging applications. Conventional IAs rely on several matching resistors which occupies a lot of silicon area, the input and output common mode voltages are exactly same and the maximum applied signal amplitude is limited by internal node voltage swings. The present proposal eliminates the need for matching resistors by processing signals in the current mode. Hence input amplitudes are no longer limited by the voltage headroom and input and output common-mode voltages can be independent. An amplifier with a differential gain greater than 52dB and a common mode rejection ratio (CMRR) greater than 120dB has been implemented in 65nm CMOS Technology and Post layout simulations were presented. The total circuit occupies 4500um2 silicon area and circuit consumes ~260μA from 1.8V power supply.Published here Open Access on RADAR -
R Nagulapalli, K Hayatleh, S Barker, S Zourob, N Yassine, 'An OTA Gain Enhancement Technique for low power biomedical applications'
Analog Integrated Circuits and Signal Processing 95 (3) (2018) pp.387-394
ISSN: 0925-1030 eISSN: 1573-1979AbstractThe performance requirement of an operational trans-conductance amplifier (OTA) for the high gain and low power neural recording frontend has been addressed in this paper. A novel split differential pair technique is proposed to improve the gain of the OTA without any additional bias current requirements. The design demonstrates a significant performance enhancement when compared to existing techniques, such as gain-boosting and recycling. A qualitative and quantitative treatment is presented to explore the impact of the split ratio on the performance parameters of gain, bandwidth, and linearity. A prototype implemented in TSMC 65 nm CMOS technology achieved 68 dB open loop-gain (13 dB higher than the conventional circuit) and a 17 kHz 3-dB bandwidth. A linearity of − 62 dB has been achieved with 7 mV pk–pk signal at the input. The circuit operates from a 1 V supply and draws 0.6 uA static current. The prototype occupies 3300 um2 silicon area.Published here Open Access on RADAR -
S Zourob, K Hayatleh, S Barker, R Nagulapalli, N Yassine, R Ramsbottom and F J Lidgey, 'Increasing Signal to Noise Ratio and Minimizing Artefacts in Biomedical Instrumentation Systems'
Analog Integrated Circuits and Signal Processing 95 (3) (2018) pp.403-408
ISSN: 0925-1030 eISSN: 1573-1979AbstractCapturing a near-perfect, artefact free signal is an ideal of biomedicine. However, this depends on the removal of different types of artefact, all of which can be considered unwanted noise on the desired signal. Failure to remove artefacts could lead to a clinical misinterpretation of the results. All medical equipment such as electrocardiogram systems which use electrodes attached to patients suffer from artefacts, with effects ranging from minor blurring to significant distortion of the output signal(s). For this reason, it is important to identify how artefacts can influence the output signal. In this paper, we propose a new technique to detect and minimise movement artefacts using strain gauges embedded into the electrodes.Published here Open Access on RADAR -
N. Yassine, S. Barker, K. Hayatleh, B. Choubey, R. Nagulapalli, 'Simulation of Driver Fatigue Monitoring via Blink Rate Detection, using 65nm CMOS Technology'
Analog Integrated Circuits and Signal Processing 95 (3) (2018) pp.409-414
ISSN: 0925-1030 eISSN: 1573-1979AbstractThis paper proposes a system to detect and measure blink rate to determine fatigue levels. The method involved analysing specific frames to determine that a blink occurred, and then monitoring the time between successive blinks. The program was simulated in python using a Raspberry Pi Zero and a standard USB camera. For the blink rate detection block, a gate level schematic was implemented in Cadence software using 65nm CMOS technology. The design was based around an asynchronous 6-bit based edge counter which was designed using D-flip-flops. The simulation calculated the average blink rate and compared this to the most recent blink rate. The outcome would determine if an alarm signal should be sent to the alarm. The system consumed 130uA from a 1.2V power supply.Published here Open Access on RADAR -
Nagulapalli R, Hayatleh K, Barker S, Raparthy S, Yassine N, Lidgey FJ, 'A 0.6V MOS-only voltage reference for bio-medical applications with 40ppm/0c temperature drift'
Journal of Circuits, Systems, and Computers 27 (8) (2018)
ISSN: 0218-1266 eISSN: 1793-6454AbstractThis paper exploits the CMOS beta multiplier circuit to synthesize a temperature independentPublished here Open Access on RADAR
voltage reference suitable for low voltage and ultra-low power bio-medical applications. The
technique presented here uses only MOS transistors to generate PTAT and CTAT currents. A selfbiasing technique has been used to minimize the temperature and power supply dependency. A prototype in 65nm CMOS has been developed and occupies 0.0039mm, and at room temperature it generates a 204mV reference voltage with 1.3mV drift over a wide temperature range (from -40 to 1250C). This has been designed to operate with a power supply voltage down to 0.6V and consumes 1.8uA current from the supply. The simulated temperature coefficient is 40ppm/0C. -
Nagulapalli R, Hayatleh K, Barker S, Raparthy S, Lidgey FJ, 'A CMOS blood cancer detection sensor based on frequency deviation detection.'
Analog Integrated Circuits and Signal Processing 92 (3) (2017) pp.437-442
ISSN: 0925-1030 eISSN: 1573-1979AbstractThis paper proposes a technique to detect Leukaemia (blood cancer) based on the frequency modulation of a relaxation oscillator by changes in the dielectric constant of blood cells. A novel 16-bit frequency detector with a digital output has been proposed to detect the frequency difference between two oscillators based on healthy blood and Leukaemic blood. A circuit has been designed, to operate on a 1.2V supply, post layout simulations shows 0.35mA current consumption. The chip Area including pads~0.6mm∗0.45mmPublished here Open Access on RADAR -
Tammam AA, Hayatleh K, Barker S, Terzopoulos N, 'Theoretical Study of the Circuit Architecture of the Basic CFOA and Testing Techniques'
International Journal of Electronics 103 (9) (2016) pp.1475-1497
ISSN: 0020-7217 eISSN: 1362-3060AbstractPublished here Open Access on RADARThis paper examines the closed-loop characteristics of the basic CFOA, and in particular, the dynamic response. Additionally, it also examines the design and advantages of the CFOA regarding its ability to provide a significantly constant closed-loop bandwidth for closed-loop voltage gain. Secondly, the almost limitless slew–rate provided by the class AB input stage that makes it superior to the VOA counterpart. Additionally; this paper also concerns the definitions and measurements of the terminal parameters of the CFOA, regarded as a ‘black box’. It does not deal with the way that these parameters are related to the properties of the active passive and active components of a particular circuit configuration. Simulation is used in terminal parameter determination: this brings with it the facility of using test conditions that would not normally prevail in a laboratory test on silicon implementations of the CFOAs. Thus, we can apply 1mA and 1mV test signals from, respectively, infinite and zero source impedances that range in frequency from d.c to some tens of GHz. Also, we assume the existence of resistors with identical Ohmic value and very high value ideal capacitors. Where appropriate, practical test methods are referred to physical laboratory prototypes.
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Tammam AA, Hayatleh K, Barker S, Ben-Esmael M, Terzopoulos N, 'Improved designs for current feedback op-amps'
International Journal of Electronics Letters 4 (2) (2015) pp.215-227
ISSN: 2168-1724AbstractThe performance of the current feedback op-amps (CFOAs) is very much determined by the input stage of CFOAs, including common-mode rejection ratio (CMRR). Two new CFOAs topologies are presented in this article: one topology uses a cascoding technique, and the second one uses a bootstrapping technique, both of which provide a much better CMRR and lower DC offset voltage than the conventional CFOAs. Moreover, the new CFOAs design exhibits an extended high frequency bandwidth, with a gain accuracy improvement. Applications requiring constant bandwidth with variable (closed loop) gain will benefit from the proposed topologies.Published here Open Access on RADAR -
Terzopoulos N, Hayatleh K, Sebu C, Lidgey FJ, Ben-Esmael M, Tammam AA, Barker S, 'Analysis and design of a high precision- high output impedance tissue current driver for medical applications'
Journal of Circuits, Systems, and Computers 23 (8) (2014)
ISSN: 0218-1266 eISSN: 1793-6454AbstractThis paper describes the design and operation of a high output impedance tissue current driver circuit, for use in medical electronics, such as Electrical Impedance Tomography (EIT). This novel architecture was designed for implementation in bipolar technology, to meet the specifications for EIT, namely operating frequency range 10 kHz–1 MHz with a target output resistance of 16 MW. Simulation results are presented, showing that the current source more than met the minimum specification for EIT.
Book chapters
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Beton L, Hughes P, Barker S, Pilling M, Fuente L, Crook NT, 'Leader-Follower Strategies for Robot-Human Collaboration' in Aldinhas Ferreira MA, Silva Sequeira J, Osman Tokhi M, Kadar EE, Singh Virk G (ed.), A World with Robots, Springer (2017)
ISBN: 9783319466651 eISBN: 9783319466675AbstractThis paper considers the impact that robot collaboration strategies have on their human collaborators. In particular, we are interested in how robot leader/follower strategies affect perceived safety and perceived intelligence, which, we argue, are essential for establishing trust and enabling true collaboration between human and robot. We propose an experiment which will enable us to evaluate the impact of leader/follower collaboration strategies on perceived safety and intelligence.Published here
Conference papers
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R. Nagulapalli, K. Hayatleh, N. Yassine, S. Barker, R. Palani, 'A 0.82V Supply and 23.4 ppm/0C Current Mirror Assisted Bandgap Reference'
(2021)
ISSN: 2688-1454 ISBN: 9781665434294AbstractPublished here Open Access on RADARTraditional BGR circuits require a 1.05V supply due to the VBE of the BJT. Deep submicron CMOS technologies are limiting the supply voltage to less than 940mV. Hence there is a strong motivation to design them at lower supply voltages. The supply voltage limitation in conventional BGR is described qualitatively in this paper. Further, a current mirror-assisted technique has been proposed to enable BGR operational at
0.82V supply. A prototype was developed in 65nm TSMC CMOS technology and post-layout simulation results were performed. A self-bias opamp has been exploited to minimize the systematic offset. Proposed BGR targeted at 450mV works from 0.82-1.05V supply without having any degradation in the performance while keeping the integrated noise of 15.2μV and accuracy of 23.4ppm/0C. Further, the circuit consumes 21μW
of power and occupies 73*32μm2 silicon area. -
Nagulapalli R, Palani RK, Agarwal S, Chatterjee S, Hayatleh K, Barker S, 'A 15uW, 12 ppm/C Curvature Compensated Bandgap in 0.85V Supply'
(2021)
ISSN: 2158-1525 ISBN: 9781728192017AbstractPublished here Open Access on RADARIn this paper, a curvature-compensated bandgap reference circuit is presented which generates 0.538V from 0.85V supply voltage. The PTAT voltage generated in the bandgap core is added to the partial CTAT voltage to generate the sub-bandgap reference, reducing the CTAT current mirror mismatch. Furthermore, this architecture eases the opamp's requirements on offset and flicker noise significantly and doesn't require sophisticated techniques, such as chopping. A novel curvature compensation scheme is proposed and validated across PVT simulations and achieves 12 ppm/°C with a single point trim. The proposed bandgap consumes a power of 15 μW and occupies an area of 7315 μm 2 in TSMC 28nm.
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Nagulapalli R, Hayatleh K, Barker S, 'A Single BJT 10.2 ppm/0C Bandgap Reference in 45nm CMOS Technology'
(2020)
ISBN: 978-1-7281-6852-4 eISBN: 978-1-7281-6851-7AbstractPublished here Open Access on RADARBandgap reference using 2 BJT devices are well explored in the literature. Usually, less number of BJT's would reduce the cost of the chip in modern CMOS technologies. A single BJT based reference was discussed here. V BE of the BJT has been used as CTAT voltage and a CMOS differential pair offset voltage based PTAT generation circuit used to generate zero temp coefficient reference. A prototype was developed in 45nm TSMC CMOS technology and post-layout simulationswere performed. Designed for a nominal voltage of 525mV with 10.2ppm/°C temperature coefficient. Its supply sensitivity is 0.4% and works with 1V power supply. The proposed solution consumes 51.8μW power from 1V power supply and occupies 2478 μm2 silicon area.
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Nagulapalli R, Hayatleh K, Barker S, 'A two-stage opamp frequency Compensation technique by splitting the 2nd stage '
(2020)
ISBN: 978-1-7281-6852-4 eISBN: 978-1-7281-6851-7AbstractPublished here Open Access on RADARIn this paper miller compensation of opamp has been explained intuitively and discussed the problems existing with this traditional way. Proposed an area/power efficient technique by splitting the second stage has been proposed. The splitting introduces an extra zero in the transfer function such that it will improve the stability. This tech was implemented in 45nm CMOS technology and simulated with Spectre. Simulation results show that the proposed circuit saves 50% of the capacitance area compared to the miller technique. The circuit draws320uA current from 1.5V supply and occupying 0.003108mm2 silicon area.
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R. Nagulapalli, K. Hayatleh, S. Barker, S Zourob, N.Yassine & B Naresh Kumar Reddy, 'A Technique to Reduce the Capacitor size in Two Stage Miller compensated opamp'
(2018)
ISBN: 9781538644300AbstractPublished here Open Access on RADARIn this paper two stage Miller compensated opamp has been discussed qualitatively and quantitatively. A modification to the conventional compensation network has been proposed, which will reduce the capacitor size hence circuit area. Transfer function for the newly proposed solution has been derived and explained the results. A prototype was developed in 65nm TSMC CMOS technology and simulation results have been presented. Amplifier achieved 60dB low frequency gain, 12MHz bandwidth and 55° phase margin while consuming 650uW power from 1.2V power supply. Circuit occupies 5348um 2 silicon area.
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R. Nagulapalli, K. Hayatleh, S. Barker, S Zourob, N.Yassine & B N Kumar, 'High Performance Circuit Techniques for Neural Front-End design in 65nm CMOS'
(2018)
ISBN: 9781538644300AbstractPublished here Open Access on RADARIntegrated low noise neural amplifiers become recently practical in CMOS technologies. In this paper, a low
noise OTA technique has been proposed while keeping the power consumption constant. A capacitive feedback, ac coupled 46dB amplifier with high pass cutoff frequency close to the 90Hz has been achieved. The proposed amplifier has been implemented in 65nm CMOS technology; at room temperature circuit consumes 323uA current from 1.2V power supply. The circuit occupies 2627um2 silicon area. -
Nagulapalli R, Hayatleh K, Barker S, Zourob S, Yassine N, Venkatareddy A, 'A compact high gain opamp for Bio-medical applications in 45nm CMOS technology'
(2018) pp.231-235
ISBN: 9781509037749AbstractIn this paper a low opamp compensation technique suitable for the bio-medical application has been proposed and intuitive explained the existing compensation techniques. The Present technique relies on the passive damping factor control rather power hungry damping. Implemented in 45nm CMOS technology and simulated with Spectre. Simulation results shows that 100dB dc gain, well compensated 25MHz bandwidth opamp while driving a 1pF capacitive load. Draws with 12uW power consumption from 1V supply and occupying 0.004875mm2 silicon area.Published here Open Access on RADAR -
Nagulapalli R, Hayatleh K, Barker S, Zourob S, Yassine N, Sridevi S, 'A bio-medical compatible Self-bias opamp in 45nm CMOS technology'
(2017)
ISBN: 9781538617168AbstractIn this paper a low power, high gain self bias opamp suitable for biomedical applications has been described. A novel trans conductance boosting technique is introduced without having any additional power consumption. A simple technique of biasing the opamp has been introduced for very low offset and without having any requirement for external reference circuit. A prototype of two stage amplifier design presented to verify the proposed technique and described its robustness across PVT variations by showing simulation results. The design is implemented in 45nm CMOS technology and simulated with Spectre. Simulation results show that the proposed opamp exhibits FOM of 625 and 2 times better than state of art. The circuit consumes 26uW from 1.5V supply and occupying 0.00282mm2 silicon area.Published here -
Barker S, Izadi H, Crook NT, Hayatleh K, Rolf M, Hughes P, Fellows N, 'Natural head movement for HRI with a muscular-skeletal head and neck robot'
(2017) pp.587-592
eISSN: 1944-9437 ISBN: 9781538635186AbstractThis paper presents a study of the movements of a humanoid head-and-neck robot called Eddie. Eddie has a musculo-skeletal structure similar to that found in human necks enabling it to perform head movements that are comparable with human head movements. This study compares the movements of Eddie with those of a more conventional robotic neck structure and with those of a human head. Results show that Eddie’s movements are perceived as significantly more natural and by trend more lifelike than the conventional head’s. No differences were found with respect to the impression of humanlikeness, consciousness, and elegance.Published here Open Access on RADAR -
Nagulapalli R, Hayatleh K, Barker S, Zourob D, Venkatreddy S, 'A CMOS technology friendly Wider bandwidth Opamp Frequency Compensation'
(2017)
ISBN: 9781509032396AbstractIn this a paper a novel CMOS technology friendly opamp compensation has been presented and explained intuitively miller compensation pole splitting. Present technique utilizes grounded capacitor and having better PSRR. Open loop transfer functions have been derived to show the proposed technique is low power for the same bandwidth. Implemented in 65nm CMOS technology and simulated with Spectre. Simulation results shows that the proposed opamp achieves FOM ~83333.Opamp consumes 25uA from 1V supply and occupying 5184um2 silicon area.Published here -
Nagulapalli R, Hayatleh K, Barker S, Zourob S, Venkatreddy S, 'A novel current reference in 45nm cmos technology'
(2017)
ISBN: 9781509032396AbstractIn this paper a novel CMOS temperature and supply voltage independent current reference has been proposed. This design is based on the subtraction of two scaled version PTAT (proportional to absolute temperature) currents to provide a temperature independent current reference. The design was simulated with Spectre, and implemented in 45nm CMOS technology. Simulation results shows that the proposed current reference achieves temperature coefficient of 22ppm/0C against temperature variation of -400C –1200C and line sensitivity of 337ppm/V against supply variation of 0.6–1.8V, while consuming 135uW from 1.8V supply and occupying 5184um2Published here Open Access on RADAR -
Nagulapalli R, Hayatleh K, Barker S, Zourob S, Yassine N, Sridevi S, 'A microwatt low voltage bandgap reference for bio-medical applications'
(2017) pp.61-65
ISBN: 9781509067015AbstractIn this paper a microwatt low voltage bandgap reference suitable for the bio-medical application. The Present technique relies on the principle of generating CTAT and PTAT without using any (Bipolar Junction Transistor) BJT and adding them with a proper scaling factor for minimal temperature sensitive reference voltage. Beta multiplier reference circuit has been explored to generate CTAT and PTAT. Implemented in 45nm CMOS technology and simulated with Spectre. Simulation results shows that the proposed reference circuit exhibits 1.2% variation at nominal 745mV output voltage. The circuit consumes 16uW from 0.8V supply and occupying 0.004875mm2 silicon area.Published here Open Access on RADAR -
Barker S, Fuente L, Hayatleh K, Fellows N, Steil JJ, Crook N, 'Design of a Biologically Inspired Humanoid Neck'
(15820238) (2015) pp.25-30
ISBN: 978-1-4673-9674-5 eISBN: 978-1-4673-9675-2AbstractThis paper presents the design of a novel anthropomorphic robotic neck. It mimics the range of movements found in the human neck, actuated by pneumatic artificial muscles. The proposed humanoid neck simulates the anatomical functionality and structure of a human neck. Specifications are made according to biological, anatomical and behavioural data. The preliminary results show that the proposed humanoid neck is able to deliver the range of movements and head velocities comparable to those observed in human necks. These results also demonstrate that biologically inspired musculoskeletal robotic systems represent a reliable and robust platform to investigate motion development.Published here Open Access on RADAR