Dr Abusaleh Jabir
DPhil (Oxon)
University Reader
School of Engineering, Computing and Mathematics
Role
I am a University Reader with the School of Engineering, Computing, and Mathematics. I am highly active in innovative research and development. In addition to my research duties, I am also involved in teaching and course management, where I have the role of:
- Subject Coordinator for our Information Technology Management for Business degree.
- Subject Expert and Faculty Liaison Manager for our Institutional Partnership Program with the Metropolitan College in Greece where we are running a program on Information Technology for Business.
Research
I established the Advanced Reliable Computer Systems (ARCoS) reseasrch group several years ago, which I also lead. This self-sustaining group specialises in research and innovation in the design, tests, and verification of reliable and fault tolerant electronic hardware, with special focus on the emerging memristor based nanotechnology. Specifically in the memristor technology this group is working on reliable high density memory and sensor array design, low power high performance logic design, as well as neuromorphic and artificial neural network aspects of memristive devices.
I have done my doctoral (DPhil) degree in Computing from the University of Oxford. My research track record comprises more than 80 fully reviewed publications, best paper awards, book chapters, a number of patents, keynote paper, etc. I am also serving as member of program committee for IEEE conferences.
My research interests include:
- Reliable and fault tolerant hardware designs;
- Electronic design automation, especially automatic CAD tools for hardware synthesis;
- Sensing and processing at the edge;
- Physical uncloneability in electronic hardware for authentication;
- Emerging technologies such as memristive devices.
I have carried out innovative research in a wide range of areas from Error and Attack Tolerant Electronic Hardware Designs to Automatic Synthesis and Optimisation of Electronic Hardware from its high level specs. In addition to publishing the results in premier journals and conferences, patents were also filed. Some of my filed and granted patents are listed below.
- Patent No. EU 17706875.6-1203. Memristive Multifunction Logic Architecture. Granted in September 2019.
- Patent No. number US 61/608,694 and GB 1114831.9. Cross Parity and BCH code based error tolerant electronic circuit design. Filed in March 2012 and August 2011. Now granted in various parts of the world, e.g as 10-201548 in South Korea.
- Patent No. EU PCT/GB2007/004206. GfXpressTM: An Efficient Approach to Synthesis and Optimization of GF(2m) Polynomials in Hardware. Now granted in various parts of the world (Filed in October 2006).
- Patent No. GB 1914221.5. Reconfigurable Memristive Architecture for Logic Operations and Process Variation Aware Sensing. Filed in October 2019.
- Patent No. GB 1905392.5. A Lightweight Physically Uncloneable Memristive Architecture for Secure Backup and Authentication. Filed in April 2019.
- Patent No. GB 1616837.9. Memristive Sensor Array. Filed in October 2016.
Further information about these inventions can be obtained from our Research and Business Development Office or by contacting me directly.
The Advanced Reliable Computer Systems Group
Our vision is to conceive innovative electronic circuits and systems, encompassing both mature and emerging technologies, with the objective of achieving much higher security, reliability, and efficiency than possible with the currently available systems. We believe that no single technology can satisfy these requirements on their own due to various shortcomings in each technology. For example, the existing technology landscape is dominated by the Metal Oxide Semiconductor Transistor (MOST) technology, which has well established itself as a highly scalable and power efficient technology. However, MOST is reaching its limits in scalability and various parasitic effects, including capacitance, as well as vulnerability to radiations and hardware attacks have become more prominent. Therefore, to achieve this we are committed to a complete rethink (with a possible paradigm shift) of the state-of-the-art for enhancing the currently achievable performances and capabilities by exploring ‘alternative’ and emerging technologies. Our vision is consistent with the requirements of the Internet of Things (IoT), Edge Computing, as well as cyber security and space explorations, where the requirements of secure, efficient, reliable and robust electronic systems are paramount. To this end, we are exploring various emerging devices such as memristors for ground-breaking applications in chemical sensing, light-weight and highly resilient authentication and uncloneable hardware as well as sensing and processing at the edge, owing to their unique properties and numerous advantages.
This self-sustaining group has enjoyed research funding from various sources, e.g. the Ministry of Defence UK (MoD-CDE DSTL), the EPSRC, Finance South East.
The group comprises a number of PhD students, Research Associates, and collaborative partners and colleagues from both industries as well as other institutions.
My former PhD students, some of whom are also co-inventor of our patents, are employed in world leading Semiconductor Chip Design and Automotive Industries. Dr Adeyemo Adedotun, who completed his PhD with me in Reliable Memristive Arrays (Title: Design and Analysis of Memristor Based Reliable Crossbar Architectures), now works with Infineon Technologies, UK. Dr Mahesh Poolakkaprambil, who completed his PhD with me in Error Tolerant Electronic Hardware (Title: Multiple Bit Error Correcting Architectures Over Finite Fields), leads The Department of Microcontroller Series Development at Continental Teves AG & Co in Germany.
Research projects
One of my current live projects is: MONITOR: A Self-Reparable Memristive Gas Sensor Array funded by the Leverhulme Trust, UK. This project is in collaboration with Dr Marco Ottavi and Dr Eugenio Martinelli with the University of Rome Tor Vergata, Italy. Here we are exploring the gas sensing properties of memristive devices and working on innovative self-repairable architectures for sensing multiple gases.
Groups
Projects
- Design and Analysis of Memristor Based Reliable Crossbar Architectures
- Design, Analysis and Testing of Memristive Logic and Authentication Architectures
- Design, Test and Analysis of Error Tolerant Memristive Neural Networks
- Error Tolerant Electronic Hardware Design
- Finite Field Realization of Efficient and Fault Tolerant VLSI Structures for Cryptography
- MONITOR: A self-repairable memristive gas sensor array
Publications
Journal articles
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Khandelwal S, Ottavi M, Martinelli E, Jabir A, 'Low Power Memristive Gas Sensor Architectures with Improved Sensing Accuracy'
Journal of Computational Electronics 21 (2022) pp.1005-1016
ISSN: 1569-8025 eISSN: 1572-8137AbstractPublished here Open Access on RADARMemristive devices, traditionally considered for memory, logic, and neuromorphic systems, are exhibiting many interesting properties for applications in a variety of areas, such as in sensing chemicals. However, any realistic approach based on these devices must take into account their susceptibility to process and parametric variations. When used for sensing purposes this, together with wire resistance, can significantly degrade their sensing accuracy. To this end, we propose novel memristive gas sensor architectures that can significantly reduce these effects in a predictable manner, while improving accuracy and overall power consumption. Additionally, we show that in the absence of gasses this architecture can also be configured to realize multifunction logic operations as well as Complementary Resistive Switch with low hardware overhead, thereby enhancing resource reusability. We also present a method for further improving power consumption and measurability by manipulating a device's internal barrier. Our results show that the proposed architecture is significantly immune to process and parametric variations compared to a single sensor and almost unaffected by wire resistance, while offering much higher accuracy and much lower power consumption compared to existing techniques.
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Anu Bala
Xiaohan Yang
Adedotun Adeyemo
Abusaleh Jabir, 'Efficient and Low Overhead Memristive Activation Circuit for Deep Learning Neural Networks'
Journal of Low Power Electronics 15 (2) (2019) pp.214-223
ISSN: 1546-1998 eISSN: 1546-2005AbstractPublished here Open Access on RADARAn efficient memristor MIN function based activation circuit is presented for memristive neuromorphic systems, using only two memristors and a comparator. The ReLU activation function is approximated using this circuit. The ReLU activation function helps to significantly reduce the time and computational cost of training in neuromorphic systems due to its simplicity and effectiveness in deep neural networks. A multilayer neural network is simulated using this activation circuit in addition to traditional memristor crossbar arrays. The results illustrate that the proposed circuit is able to perform training effectively with significant savings in time and area in memristor crossbar based neural networks.
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Adedotun A, Mathew J, Jabir A, Di Natale C, Martinelli E, Ottavi M, 'Efficient Sensing Approaches for High-density Memristor Sensor Array'
Journal of Computational Electronics 17 (3) (2018) pp.1285-1296
ISSN: 1569-8025 eISSN: 1572-8137AbstractRecent research shows ever growing interest in the potential applications of memristive devices.Published here Open Access on RADAR
Among the many proposed fields, sensing is one of the most interesting as it could lead to unprecedented sensor density and ubiquity in electronic systems. In this paper, a framework for efficient gas detection using memristor crossbar array is proposed and analysed. A novel Verilog-A based memristor model that emulates the gas sensing behaviour of doped metal oxides is developed for simulation and integration with design automation tools. Using this model, we propose and analyse three different gas detection structures based on array of memristor-based sensors. Gas presence together with some of its properties can be detected using resistance
changes and spatial information from one or group of memristive sensors. Our simulation results show that depending on the organisation of the memristive elements and the sensing method, the response of the sensor varies providing a broader design space for future designers. For instance, with a 8 × 8 memristor sensor array, there is a ten times improvement in the accuracy of the sensor’s response when compared with a single memristor sensor but at the expense of extra area overhead. -
Adeyemo A, Jabir A, Mathew J, 'Minimising impact of wire resistance in low-power crossbar array write scheme'
Journal of Low Power Electronics 13 (4) (2017) pp.649-660
ISSN: 1546-1998 eISSN: 1546-2005AbstractThis paper presents a circuit level analysis of write operation in memristor crossbar memoryOpen Access on RADAR
array with and without line resistance. Three write schemes: floating line, V/2 and V/3 are investigated. Analysis shows that floating line scheme could also be considered reliable in arrays with aspect ratio of 1:1 and negligible line resistance just like the latter two schemes. Further analysis also shows that high density crossbar structures cannot be designed using any of the three schemes with worst case line resistance and data distribution within the array. To solve this problem, we propose a voltage compensating technique for write voltage degradation caused by line resistance during write operation on crossbar array. This technique is able to enhance write voltage in the presence of worst case line resistance and thus enable the design of higher density and reliable crossbar array. -
Yang X, Adeyemo A, Bala A, Jabir A, 'Novel techniques for memristive multifunction logic design'
Integration 65 (2017) pp.219-230
ISSN: 0167-9260 eISSN: 1872-7522AbstractWe present novel techniques for realising reliable low overhead logic functions and more complex systems based on the switching characteristics of memristors. Firstly, we show that memristive circuits have inherent properties for realising multiple valued MIN-MAX operations over the post algebra. We then present an efficient hybrid 1T-4M logic architecture for dual XOR/AND and XNOR/OR functionality, which can be seamlessly integrated with the existing CMOS technology. Although memristors are usually considered to operate at lower frequencies, however, recent advances in technology show their potentiality at high frequencies. To this end, we also explore the effects of high frequencies on their performance and thereby propose reliable high frequencyPublished here Open Access on RADAR
design techniques based on our 1T-4M architectures. Experimental results, based on the design of full adders and multipliers over GF, show that the proposed designs require significantly lower power and overhead while maintaining reliable performance at low as well as at high frequencies compared to the existing techniques. -
Yang X, Adeyemo A, Jabir AM, Mathew J, 'A High Performance Single Cycle Memristive Multifunction Logic Architecture'
Electronics Letters 52 (11) (2016) pp.906-907
ISSN: 0013-5194 eISSN: 1350-911XAbstractWe present a low complexity high performance memristive multifunction logic architecture for low power high frequency operations in a single cycle, which does not require additional controlPublished here Open Access on RADARinput/logic and multicycle setup/operation. It can be seamlessly integrated with the existing CMOS technology with just 1T-4M design and without additional overhead. Our technique can realise both XOR/AND or XNOR/OR operations simultaneously. Experimental results show that our technique significantly outperforms both CMOS and existing hybrid memristor-CMOS based designs in terms of chip area, power consumptions, and reliable performance especially at high
frequencies. With the help of full adder designs, we also demonstrate that the multifunctionality of our architecture can result in highly compact designs.
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Poolakkaparambil M, Mathew J, Jabir AM, Pradhan DK, 'A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF (2m)'
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (8) (2015) pp.1448-1458
ISSN: 1063-8210AbstractPublished hereThis paper presents a novel low-complexity cross parity code, with a wide range of multiple bit error correction capability at a lower overhead, for improving the reliability in circuits over GF(2m). For an m input circuit, the proposed scheme can correct m ≤ Dw≤ 3m/2 -1 multiple error combinations out of all the possible 2m - 1 errors, which is superior to many existing approaches. From the mathematical and practical evaluations, the best case error correction is m/2 bit errors. Tests on 80-bit parallel and, for the first time, on 163-bit Federal Information Processing Standard/National Institute of Standards and Technology (FIPS/NIST) standard word-level Galois field (GF) multipliers, suggest that it requires only 106% and 170% area overheads, respectively, which is lower than the existing approaches, while error injection-based behavioral analysis demonstrates its wider error correction capability.
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Rahaman H, Mathew J, Jabir A, Pradhan D, 'Simplified bit parallel systolic multipliers for special class of Galois field (2m) with testability'
IET Computers & Digital Techniques 4 (5) (2010) pp.428-437
ISSN: 1751-8601AbstractPublished hereThis study presents a simplified structure of bit parallel systolic multiplier over Galois fields (GFs) over the set GF(2m) suitable for cryptographic hardware implementation. A redundant standard basis representation with the irreducible all one polynomial is considered. The systolic multiplier consists of (m+1)2 identical cells, each consisting of one two-input AND gate, one two-input XOR gate and two one-bit latches. This architecture is well suited to very large-scale integration implementation because of its regularity modular structure and unidirectional data flow. The proposed multipliers have clock cycle latency of (m +1). This architecture has a total reduction of m2 D-flip-flops compared to earlier bit parallel systolic multiplication architecture. As the finite-field multiplier is one of the complex blocks in cryptographic hardware and need secure testability to avoid unwanted access into the on-chip security blocks, the authors also introduce an on-chip testing scheme. The authors propose a test generation technique for detecting stuck-at fault (SAF), transition delay fault (TDF), stuck-open fault (SOF) and path delay faults (PDFs) at the gate and cell level in the systolic architecture. The authors also show that realistic sequential cell fault can be detected only by 12 single input change test vectors in the complete systolic multiplier over GF(2m). The proposed technique derives test vectors from the cell expressions of systolic multipliers without any requirement of an automatic test pattern generation tool. The complete systolic architecture is C-testable for SAF, TDF, SOF and PDF with only 12 constant tests. The test vectors are independent of the multiplier size. The test set provides 100% single SAF, TDF, SOF and PDF coverage.
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Argyrides C, Pradhan D, Mathew J, Jabir A, Rahaman H, 'On the synthesis of Bit Parallel Galois Field Multipliers with On-line SEC and DED'
International Journal of Electronics 96 (11) (2009) pp.1161-1173
ISSN: 0020-7217 eISSN: 1362-3060AbstractIn this paper, we present a systematic method for designing single error correcting (SEC) and double error detecting finite field (Galois field) multipliers over GF(2m). The detection and correction are done on-line. We use multiple Parity Predictions to detect and correct errors. Specifically, a structural approach is first presented. The predicted parity bits are derived from the primitive polynomials for generating the fields. Further, a hybrid approach is presented where the multipliers and PP circuits are synthesised, and the decoding and correction circuits are structurally combined to form the complete error correcting designs. Although the article considers only a finite field multiplier, without loss of generality, the technique could be applied to any combinational logic circuit. Our technique, when compared with existing techniques, gives better performance. We show that our SEC multipliers over GF(2m) require about 100% extra hardware, whereas with the traditional SEC techniques, such as the triple-modular redundancy (TMR), this figure is more than 200%. Moreover, the multiple bit error detection and correction using multiple Hamming code were also introduced.Published here -
Mathew J, Jabir A, Rahaman H, Pradhan D, 'Single error correctable bit parallel multipliers over GF(2^m)'
IET Computers & Digital Techniques 3 (3) (2009) pp.281-288
ISSN: 1751-8601AbstractPublished hereMotivated by the problems associated with soft errors in digital circuits and fault-related attacks in cryptographic hardware, a systematic method for designing single error correcting multiplier circuits is presented for finite fields or Galois fields over GF(2m). Multiple parity predictions to correct single errors based on the Hamming principles are used. The expressions for the parity prediction are derived from the input operands, and are based on the primitive polynomials of the fields. This technique, when compared with existing ones, gives better performance. It is shown that single error correction (SEC) multipliers over GF(2m) require slightly over 100% extra hardware, whereas with the traditional SEC techniques, this figure is more than 200%. Since single bit internal faults can cause multiple faults in the outputs, this has also been addressed here by using multiple Hamming codes with optimised hardware.
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Jabir A, 'C-Testable Bit-Parallel Multipliers Over GF(2m)'
Transactions on Design Automation of Electronic Systems 13 (1) (2008) pp.1-18
ISSN: 1084-4309AbstractWe present a C-testable design of polynomial basis (PB) bit-parallel (BP) multipliers over GF(2m) for 100% coverage of stuck-at faults. Our design method also includes the method for test vector generation, which is simple and efficient. C-testability is achieved with three control inputs and approximately 6% additional hardware. Only 8 constant vectors are required irrespective of the sizes of the fields and primitive polynomial.We also present a Built-In Self-Test (BIST) architecture for generating the test vectors efficiently, which eliminates the need for the extra control inputs. Since these circuits have critical applications as parts of cryptography (e.g., Elliptic Curve Crypto (ECC) systems) hardware, the BIST architecture may provide with added level of security, as the tests would be done internally and without the requirement of probing by external testing equipment. Finally we present experimental results comprising the area, delay and power of the testable multipliers of various sizes with the help of the Synopsys tools using UMC 0.18 micron CMOS technology library.Published here -
Rahaman H, Mathew J, Pradhan D, Jabir A, 'Derivation of reduced test vectors for bit parallel multipliers over GF(2^m)'
IEEE Transactions on Computers 57 (9) (2008) pp.1289-1294
ISSN: 0018-9340AbstractThis paper presents an algebraic testing method for detecting stuck-at faults in the polynomial basis (PB) bit parallel (BP) multiplier circuits over GF(2m). The proposed technique derives the test vectors from the expressions of the inner product (IP) variables without any requirement of ATPG tool. This low complexity testing method requires (2m+1) test vectors for detect-ing single stuck-at faults in the AND part and multiple stuck-at faults in EXOR part of the multiplier circuits. The test vectors are independent of multiplier's structure proposed in [11] but dependant on m. For the multiplier circuits, the test set is found to be smaller in size than the ATPG-generated test set. The test set provides 100% single stuck-at fault coverage.Published here -
Jabir A, Pradhan D, Mathew J, 'GfXpress: A technique for synthesis and optimization of GF(2m) polynomials'
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27 (4) (2008) pp.698-711
ISSN: 0278-0070AbstractThis paper presents an efficient technique for synthesis and optimization of the polynomials over GF(2m), where to is a nonzero positive integer. The technique is based on a graph-based decomposition and factorization of the polynomials, followed by efficient network factorization and optimization. A technique for efficiently computing the coefficients of the polynomials over GF(pm), where p is a prime number, is first presented. The coefficients are stored as polynomial graphs over GF(pm). The synthesis and optimization is initiated from this graph-based representation. The technique has been applied to minimize multipliers over the fields GF(2k), where k = 2,...,8, generated with all the 51 primitive polynomials in the 0.18-mum CMOS technology with the help of the Synopsys design compiler. It has also been applied to minimize combinational exponentiation circuits, parallel integer adders and multipliers, and other multivariate bit- as well as word-level polynomials. The experimental results suggest that the proposed technique can reduce area, delay, and power by significant amounts. We also observed that the technique is capable of producing 100% testable circuits for stuck-at faults.Published here -
Jabir A, Pradham D, Singh A, Rajaprabhu T L, 'A technique for representing multiple-output binary functions with applications to verfication and simulation'
IEEE Transactions on Computers 56 (8) (2007) pp.1133-1145
ISSN: 0018-9340 eISSN: 1557-9956AbstractThis paper presents a technique for representing multiple output binary and word-level functions in GF(N) ($N=p^m$, p a prime number and m a nonzero positive integer) based on decision diagrams (DD). The presented DD is canonical and can be made minimal with respect to a given variable order. The DD has been tested on benchmarks including integer multiplier circuits and the results show that it can produce better node compression (more than an order of magnitude in some cases) compared to shared BDDs. The benchmark results also reflect the effect of varying the input and output field sizes on the number of nodes. Methods of graph-based representation of characteristic and encoded characteristic functions in GF(N) are also presented. Performance of the proposed representations has been studied in terms of average path lengths and the actual evaluation times with 50,000 randomly generated patterns on many benchmark circuits. All these results reflect that the proposed technique can out perform existing techniques.Published here -
Jabir A, Pradhan D, 'A graph-based unified technique for computing and representing co-efficients over finite fields'
IEEE Transactions on Computers 56 (8) (2007) pp.1119-1132
ISSN: 0018-9340AbstractThis paper presents the generalized theory and an efficient graph-based technique for the calculation and representation of coefficients of multivariate canonic polynomials over arbitrary finite fields in any polarity. The technique presented for computing coefficients is unlike polynomial interpolation or matrix-based techniques and takes into consideration efficient graph-based forms which can be available as an existing resource during synthesis, verification, or simulation of digital systems. Techniques for optimization of the graph-based forms for representing the coefficients are also presented. The efficiency of the algorithm increases for larger fields. As a test case, the proposed technique has been applied to benchmark circuits over GF2. The experimental results show that the proposed technique can significantly speed up execution time. Finite or Galois fields, decision diagrams, coefficients, polynomials.Published here
Books
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Raj B, Himani A, Khandelwal S, Jabir A, (ed.), Nanoscale Memristor Device and Circuits Design, Elsevier Publishers (2023)
ISBN: 9780323907934 eISBN: 9780323998116AbstractPublished hereDr Abusaleh Jabir, with Dr Balwinder Raj, Prof Ahmed Hemani (KTH Sweden), and Dr Saurabh Khandelwal, edited and authored a book "Nanoscale Memristor Device and Circuits Design" which is now published with the Elsevier Publishers (Nanotechnology Series). This book addresses some of the cutting edge research carried out and the key challenges in this emerging technology with applications in memory and logic design, neuromorphic and in-memory computing, chemical sensing, and cybersecurity. Four of the twelve chapters in this book are co-authored by Dr Jabir's former and current doctoral students with him.
Conference papers
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Xiaohan Y, Khandelwal S, Jiang A, Jabir A, 'A Modelling Attack Resistant Low Overhead Memristive Physical Unclonable Function'
(2020)
AbstractPublished here Open Access on RADARMemristors are finding applications in memory, logic, neuromorphic systems, and data security. To this end, we leverage the non-linear behaviour of memristors to devise a low overhead physical unclonable function using a memristive chaos circuit in conjunction with a non-linear memristive encoder. We demonstrate the effectiveness of this architecture in Challenge-Response-Pair based authentication, and for its physical uncloneability. This architecture is highly versatile and can be implemented with a single encoder or a number of encoders running in parallel, each one with its own merit, for extending the sizes of CRPs. To demonstrate its effectiveness, we subject the architecture to machine learning based modelling attacks e.g. Logistic Regression, Support Vector
Machines, Random Forest, as well as Artificial Neural Network classifiers. We found out that the proposed PUF architecture provides better resistance to such attacks, even for smaller bit sizes and at reduced overheads. -
Gupta V, Pellegrini D, Khandelwal S, Jabir A, Kvatinsky S, Martinelli E, Natale C, Ottavi M, 'Sensing with Memristive Complementary Resistive Switch: Modelling and Simulations
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(2020)
AbstractPublished here Open Access on RADARSensors give factual and process information about the environment or other physical phenomena. Sensing using memristors has been recently introduced for its potential for high density integration and miniaturization. Complementary Resistive Switch (CRS) based sensor provides an extremely efficient crossbar array that reduces the sneak current. The objective of this paper is to introduce and evaluate a circuit model for sensing using memristive complementary resistive switch. We introduce a reliable SPICE implementation of memristor model that captures the sensing behaviour of memristor. Our simulation results also validate the SPICE model for CRS sensing architecture, whose parameters could be easily adapted to match experimental data. The results also investigate the sensitivity and device behaviour of memristor and CRS sensor device in the presence of oxidizing and reducing gases of different concentration.
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Gupta V, Khandelwal S, Panunzi G, Eugenio M, Hamioui S, Jabir A, Ottavi M, 'Yield Estimation of a Memristive Sensor Array'
(2020)
AbstractPublished here Open Access on RADARThis paper proposes a method to calculate the yield of a memristor based sensor array considered as the
probability that the chip provides acceptable sensing results when the array is affected by manufacturing defects. The modeling is based on a Markov Chain approach, in which each state represents an operating chip configuration and the state transitions take into account manufacturing defects. The proposed method is applicable to evaluate the yield with different fault models to achieve the comparative yield obtained
by several redundancy allocations. -
Saurabh Khandelwal, Anu Bala, Vishal Gupta, Marco Ottavi, Martinelli Eugenio, Abusaleh Jabir, 'Fault Modeling and Simulation of Memristor based Gas Sensors'
(2019)
AbstractPublished here Open Access on RADARMemristors are an attractive option for use in future architectures due to their non-volatility, high density and low power operation. Gas sensing is one of the proposed application of memristive devices. In spite of these advantages, memristors are susceptible to defect densities due to the nondeterministic nature of nano-scale fabrication. In this paper, a novel spice memristor model incorporating fault models that emulates the gas sensing behaviour with/without faults is developed for simulation and integration with design automation tools. Our simulation results show that the proposed non-linear model detects the presence of the oxidising/reducing gas and analyses the defects/faults affecting the functionality of the sensor.
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Bala A, Adeyemo A, Yang X, Jabir A, 'Learning method for ex-situ training of memristor crossbar based multi-layer neural network'
(2018) pp.305-310
ISBN: 9781538634356 eISBN: 2157-023XAbstractPublished here Open Access on RADARMemristor is being considered as a game changer for the realization of neuromorphic hardware systems due to its similarity with biological synapse. Recent studies show that memristor crossbar can provide high density and high performance neural network hardware implementation at low power due to its physical layout, nano scale size and low power consumption feature. This paper describes the training method that can be used for the implementation of memristive multi-layer neural network with ex-situ method. We mimic the behavior of memristor crossbar in software training process to achieve more accurate and close computations to hardware. Voltage divider has been used to calculate the dot product in this method. To demonstrate the accuracy and effectiveness of this method, different patterns and non-separable functions using memristor crossbar structures are simulated. The results demonstrate that more accurate computations can be produced using this learning method for ex-situ. It also reduces the learning time of functions.
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Xiaohan Yang, Adedotun Adeyemo, Anu Bala, Abusaleh Jabir, 'Parasitic effects on memristive logic architecture'
(2017)
ISBN: 9781509064625AbstractThe most of the memristor based applications which have been proposed so far have not considered the parasitic components. In this paper, we apply a generic memristor model which includes the parasitic effects to our proposed memristive logic architectures. First, we show that the current response of the memristor has the decaying oscillation when the unit step function is applied. Then we demonstrated that our specific memristive logic structure can almost eliminate those effects which are generated by the parasitic components of the memristor. In addition, the propagation delay and the variation of the memristive XOR gate are increased because of the parasitic components. With the delay analysis on cascaded memristive logic design, the experimental results show that our 3T-4M memristive XOR architecture can build the more robust delay based memristive physical unclonable function (PUF) comparing to the existing memristive PUF.Published here Open Access on RADAR -
Adeyemo A, Jabir A, Mathew J, Martinelli E, di Natale C, Ottavi M, 'Reliable gas sensing with memristive crossbar array'
IEEE Proceedings IOLTS 2017 CFP17OLT-USB (2017) pp.244-246
ISBN: 9781538603512AbstractGas sensing is one of the proposed application field of memristive devices. We used a crossbar array of memristors as gas sensor using the HP labs fabricated TiO2 based memristor model in an attempt to improve sensing accuracy. We introduced the possibility of reliable multiple gases detection using multiple rows of memristors as separate sensor in a crossbar array. Our experimental results show that an array of memristors can minimise measurement errors as well as provide a good redundancy measure during gas sensing. Measurements taken from the sensors are also not affected by alternate current paths problem often experienced in crossbar architecture.Published here Open Access on RADAR -
Adeyemo A, Yang X, Bala A, Jabir A, 'Analytic models for crossbar write operation'
(2017) pp.313-317
ISBN: 9781509025411AbstractThis paper presents a comprehensive circuit level analysis of write operation in memristor crossbar memory array with and without line resistance. Three write schemes: floating line, 1/2 and 1/3 are investigated. Analysis shows that floating line scheme could also be considered reliable in arrays with aspect ratio of 1:1 and negligible line resistance just like the latter two schemes. Further analysis also shows that high density crossbar structures cannot be designed using any of the three schemes with worst case line resistance and data distribution within the array. These models are non-restrictive and are suitable for accurate analysis of crossbar arrays and the evaluation of their performance during write operation. The presented analysis provides the necessary design models that will assist designers in implementation of write techniques in crossbar array in future systems.Published here Open Access on RADAR -
Bala A, Adeyemo A, Yang X, Jabir A, 'High Level Abstraction of Memristor Model for Neural Network Simulation'
(2017) pp.318-322
ISSN: 2473-9413 ISBN: 9781509025411AbstractMemristor emerged as an auspicious device in the field of neuromorphic engineering due to its nanoscale size, non- volatility, scalability, fast switching, low power consumption, high density and compatability with CMOS technology. This paper unveils the first mathematical memristor modeling in C++. We also represent the implementation and training of a single layer and multilayer neural network using C++ memristor model. The memristive crossbar structure has been utilized to train the network. We successfully demonstrated linear and non-linear seperable logic functions using C++ memristor modeling in the simulation of neural network. We also demonstrated pattern classifier using single layer neural network at two different learning rates and the network performs satisfactorily at both the learning rates.Published here Open Access on RADAR -
Yang X, Adeyemo A, Bala A, Jabir A, 'Novel Memristive Logic Architectures'
(2017)
eISBN: 9781509007332AbstractWe present techniques for realising reliable logic functions and more complex systems based on the switching characteristics of memristors. First we show that memristors have inherent properties for representing multiple valued MIN-MAX logic over the post algebra. We also present efficient architectures for realising multifunction logic gates, and present a technique with hybrid 1T-4M architecture for seamless integration with existing CMOS logic. Memristors have tremendous potential for security aware hardware synthesis. To this end, we present design methods for realising highly efficient Galois Field circuits, which are widely used in crypto hardware, based on our 1T- 4M architectures. Experimental results show that our proposed design requires significantly lower power while maintaining reliable operations at high frequencies compared to the CMOS counterparts.Published here -
Adeyemo A, Yang X, Bala A, Mathew J, Jabir A, 'Analytic Models for Crossbar Read Operation'
(2016) pp.3-4
ISBN: 9781509015061AbstractResistive memories have simpler structures and are capable of producing highly dense memory through crossbar architecture without the use of access devices. Reliability however remains a problem of resistive memories especially in its basic read operation. This paper presents a comprehensive model for resistive devices in crossbar array as well as models for four crossbar read schemes. These models are non-restrictive and are suitable for accurate analytical analysis of crossbar arrays and the evaluation of their performance during read operation.Published here -
Adeyemo AA, Mathew J, Jabir AM, Pradhan DK, 'Exploring Error-Tolerant Low-Power Multiple-output Read Scheme for Memristor-Based Memory Arrays'
(2015) pp.17-20
ISBN: 978-1-5090-0312-9 eISBN: 978-1-4799-8606-4AbstractIn an effort to reduce the overall read/write power consumption in emerging memory technologies, efficient read/write schemes have recently attracted increased attention.Published hereAmong these emerging technologies is the memristor-based resistive random access memory (ReRAM) with simpler structures and capability of producing highly dense memory through the
sneak-path prone crossbar architecture. In this paper, a multiplecells read solution to reduce the overall energy consumption when reading from a memory array is considered. A closed form
expression for the noise margin effect is derived and analysis shows that there is zero sneak-path when sensing certain patterns of stored data. The multiple-cells readout method was thus used to analyse an energy efficient Inverted-Hamming (I-H) architecture capable of detecting and correcting single-bit write error in memristor-based memory array.
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Mathew J, Yang Y, Ottavi M, Brown T, Zampetti A, Di Carlo A, Jabir AM, Pradhan DK, 'Fault Detection and Repair of DSC Arrays through Memristor Sensing'
2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) (15586298) (2015) pp.7-12
ISSN: 1550-5774 ISBN: 978-1-5090-0312-9AbstractFault tolerant Photovoltaic array used for green energy systems is emerging as an important area of study because of growing emphasis on reliable design. Among various photovoltaic cells Dye Solar Cell (DSC) is a promising lowcost photovoltaic (PV) technology and high energy-conversion efficiency. Recently it has been shown that it has memristive behavior as well. To efficiently support this claim, in this paper we use experimental data to characterize DSC cell and show that it exhibits memristor state behavior and developed a SPICE model. We use memristive DSC cells as sensing devices. This enables us to identify faulty cells in regular DSC. First, we present the model from the experimental data. A search algorithm is defined to identify the faulty components of the DSC array that fulfill the first requirement of a fault tolerant design. The proposed diagnosis method utilizes recently proposed fault detection solution for efficient testing of PV cells in the presence of faults. We divide the array into segments such that any faults is detectable thereby achieving high diagnosis accuracy. The proposed diagnosis method has been validated through SPICE simulation. Spare cells are to repair the faulty array.Published here -
Adeyemo A, Mathew J, Jabir A, Pradhan D, 'Write Scheme for Multiple Complementary Resistive Switch (CRS) Cells'
(2014)
ISBN: 978-1-4799-5412-4AbstractAmongst emerging technologies with the potential to usher in a new generation of Non Volatile Memory (NVM) is the memristor. The memristor makes it possible to build simple and highly dense memory structure via cross point architecture. Memristor array however suffers exponentially from sneak path leakages as array size increases, which leads to excessive power consumption and poor data integrity. Complementary Resistive Switch (CRS) was proposed to mitigate the sneak-path problem. However, when writing into multiple cells in CRS-based memory array, the state of unselected and and half-selected cell(s) in the array are affected in an undesired way depending on the polarity, magnitude and duration of the voltage applied during the write operation. The effect of these disturbance to non-selected cell(s) is a resultant corrupted output in subsequent read operation on these cell(s). In this paper, we reviewed the basic operation of the memristor and CRS cell in relation to their application as a memory device. Finally, we implemented an improved scheme for writing alternating data patterns into multiple cells in CRS-based memory array, we also examine how the initial state of the cell affects the performance of this scheme.Published here -
Jabir A, 'Low complexity cross parity codes for multiple and random bit error correction'
(2012) pp.57-62
ISSN: 1948-3287 eISSN: 1948-3287 ISBN: 9781467310345AbstractError detection and correction which has been used in communication and memory design is becoming increasingly important in fault tolerant logic circuit design. As a result of the aggressive technology scaling, the current high-density integrated circuits are easily succumbed to faulty operations generated from many sources including stuck-at-faults, radiation induced faults, or malicious eavesdropper attacks. The currently used techniques like low-density parity-check (LDPC) and Hamming code based fault masking to mitigate bit flips in the digital circuits are either single bit error correcting or multiple error correctable with Bose-Choudhury-Hocquenghem (BCH) and Reed-solomon based methods with very large overheads. This paper introduce a novel cross code based method that can correct multiple errors with minimal compromise in error correction capability and area. The key idea of the novel method proposed in this paper is that do not correct all the errors but minimize their probability being escaped. Experimental results of the proposed methods show that the following: (1) area overhead is 101% for Hamming cross code and 106% for BCH cross code for a 90-bit finite field multiplier and (2) 150% for Hamming cross code and 170% for BCH cross codes for practically used 163-bit digit serial polynomial basis multiplier. Thus, the proposed methods are significantly efficient compared to Triple Modular Redundancy (TMR), LDPC, Hamming based methods in terms of area overhead and also the first attempted approach to a low complexity multiple error correctable digit serial multiplier to the best of the authors knowledge.Published here -
Mathew J, Rahaman H, Jabir A, Mohanty S, Pradhan D, 'On the design of different concurrent edc schemes for s-box and gf(p)'
(2010)
ISSN: 1948-3287 eISSN: 1948-3287 ISBN: 9781424464548AbstractPublished hereRecent studies have shown that an attacker can retrieve confidential information from cryptographic hardware (e.g. the secret key) by introducing internal faults. A secure and reliable implementation of cryptographic algorithms in hardware must be able to detect or correct such malicious attacks. Error detection/correction (EDC), through fault tolerance, could be an effective way to mitigate such fault attacks in cryptographic hardware. To this end, we analyze the area, delay, and power overhead for designing the S-Box, which is one of the main complex blocks in the Advanced Encryption Standard (AES), with error detection and correction capability. We use multiple Parity Predictions (PPs), based on various error correcting codes, to detect and correct errors. Various coding techniques are presented, which include simple parity prediction, split parity codes, Hamming, Hsiao, and LDPC codes. The S-Box, GF(p), and PP circuits are synthesized from the specifications, while the decoding and correction circuits are combined to form the complete designs. The analysis shows a comparison of the different approaches characterized by their error detection capability.
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Jabir A, 'On the synthesis of attack tolerant cryptographic hardware'
(2010) pp.286-291
ISBN: 9781424464692AbstractConcurrent error detection and correction is an effective way to mitigate fault attacks in cryptographic hardware. Recent work on differential power analysis shows that even mathematically-secure cryptographic protocols may be vulnerable at the physical implementation level. By measuring energy consumed by a working digital circuit, it is possible to gain valuable information about the encryption algorithms used and even the specific encryption keys. Thwarting such attacks requires a new approach to logic and physical designs. This paper presents a systematic approach to fault tolerant cryptographic hardware designs. Firstly, the effectiveness of the Hamming code based error correction schemes as a fault tolerance method in stream ciphers is investigated. Coding is applied to Linear Feedback Shift Registers (LFSR) based stream cipher implementations. The method was implemented on industrial standard stream ciphers, e.g. A5/1(GSM), E0 (Bluetooth), RC4 (WEP), and W7. The performance variation of stream cipher algorithms with error detection and correction was studied by synthesising the designs on Field Programmable Logic Arrays (FPGA) and Application Specific Integrated Circuits (ASIC). Further, we analyse hardware building blocks to minimise switching activity of a circuit over all possible inputs and input transitions by adding redundant gates and increasing the overall number of signal transitions. We also discuss the overhead and compositional properties of uniformly-switching circuits.Published here -
Jabir A, 'A Galois field based logic synthesis approach with testability'
(2008) pp.629-634
ISSN: 1063-9667 eISSN: 1063-9667AbstractIn deep-submicron VLSI, efficient circuit testability is one of the most demanding requirements. Efficient testable logic synthesis is one way to tackle the problem. To this end, this paper introduces a new fast efficient graph-based decomposition technique for Boolean functions in finite fields, which utilizes the data structure of the multiple-output decision diagrams (MODD). In particular, the proposed technique is based on finite fields and can decompose any N valued arbitrary function F into N distinct sets conjunctively and N-l distinct sets disjunctively. The proposed technique is capable of generating testable circuits. The experimental results show that the proposed method is more economical in terms of literal count compared to existing approaches. Furthermore, we have shown that the basic block can be tested with eight test vectors.Published here -
Jabir A, Pradhan D, Mathew J, 'An efficient technique for synthesis and optimization of GF(2m)'
(2007) pp.151-157
AbstractThis paper presents an efficient technique for synthesis and optimization of polynomials over GF(2m), where m is a non-zero positive integer. The technique is based on a graph-based decomposition and factorization of polynomials over GF(2m), followed by efficient network factorization and optimization. A technique for efficiently computing coefficients over GF(pm), where p is a prime number, is first presented. The coefficients are stored as polynomial graphs over GF(pm). The synthesis and optimization is initiated from this graph based representation. The technique has been applied to minimize multipliers over all the 51 fields in GF(2k), k = 2. . .8 in 0.18micron CMOS technology with the help of the Synopsys design compiler. It has also been applied to minimize combinational exponentiation circuits, and other multivariate bit- as well as word-level polynomials. The experimental results suggest that the proposed technique can reduce area, delay, and power by significant amount.Published here