Advanced Reliable Computer Systems Group (ARCoS)

Group Leader(s): Dr Abusaleh Jabir

Contact: ajabir@brookes.ac.uk

About us

We carry out world class research in the design, tests and verification of reliable and fault tolerant electronic hardware, with special focus on the emerging memristor based nanotechnology. Specifically, we carry out innovative and patented research in very low complexity error tolerant architectures compared to the state of the art.

In the memristor technology, this group is working on reliable and secure high-density memory and sensor array designs, low power high performance logic design, as well as in neuromorphic and artificial neural network designs. Since fundamentally memristors are memory elements, this group is also looking at innovative ways of securely processing, sensing, and power generation in memory and neural networks under a unified framework for high speed, low power, low latency processing of large volumes of data. The potential application areas include interconnected autonomous devices (eg autonomous robots, vehicles, smart cites and factories, etc.) and sensing and processing at the edge for Environmental Intelligence.

This self-sustaining group has secured research grants from the Leverhulme Trust, Defence Science and Technology Laboratory (MoD-DSTL), EPSRC, Finance SouthEast and generated the highest number of patentable IP within the University, which the University is currently considering for commercial exploitation. This diverse group comprises members from the UK, EU, Asia and Africa and has direct research collaborations with Higher Education Institutes (HEI) both within the UK as well as abroad. Some of the technical knowhow, knowledge and expertise generated by this group are applied in world leading industries.

Our researcher Xiaohan Yang at her desk

Leadership

Dr Abusaleh Jabir

Reader

View profile

Projects

Active projects

Project title and description Investigator(s) Funder(s) Dates

MONITOR: A self-repairable memristive gas sensor array

(Grant No. RPG-2017-344) This project is investigating innovative ways of designing self-reparable and robust chemicals sensors with memristive devices. Because of the memristive elements, the sensors are expected to sense and ‘remember’ the sensed information even after the power is removed. The project, in collaboration with the University of Rome, Italy, comprises device fabrication as well as device and systems level modelling and synthesis aspects.

Dr Abusaleh Jabir Leverhulme Trust From: September 2018
Until: September 2021

Design, Analysis and Testing of Memristive Logic and Authentication Architectures

Investigates a new generation of memristor-MOSFET hybrid multifunction logic architecture, which is capable of outperforming existing technology. The project is also investigating innovative means of data authentication based on the inherent physical properties of these devices. The project has already resulted in a number of patents and best paper awards. This project is a part of a doctoral research carried out by Ms Xiaohan Yang.

Dr Abusaleh Jabir From: September 2016

Design, Test and Analysis of Error Tolerant Memristive Neural Networks

Investigates innovative error tolerant memristive Artificial Neural Network (ANN) architectures. The idea is that even if parts of the ANN fail for an internal or external reason, the system still continues to function normally. This project first of all proposed an innovative learning technique, which essentially eliminates the so called “sneak-path” current issue in these devices, thus making the networks much more practical than was possible before. This part of the research won a best paper award at the IEEE ICUMTC 2017 in Munich, Germany. This is a part of doctoral research carried out by Ms Anu Bala.

Dr Abusaleh Jabir From: September 2016

Completed projects

Project title and description Investigator(s) Funder(s) Dates

Error Tolerant Electronic Hardware Design

(Grant No. CDE30507) Proof-of-concept for the group’s patented (Patent No. 20140229786, 9645886) hardware error correction and hardware attack mitigation IP. We developed a multiple error and attack resilient fully functional Advanced Encryption Standard (AES) hardware.

Dr Abusaleh Jabir DSTL, DASA From: September 2013
Until: December 2014

Finite Field Realization of Efficient and Fault Tolerant VLSI Structures for Cryptography

Investigated novel error detection and correction codes over finite fields, known as cross-parity codes. It corrected both soft (transient) and hard errors in various industrial strength cryptography-oriented hardware, with much improved results. The IP was granted multiple patents, which went through proof-of-concept funding. The project also culminated into successful PhD research entitled, “Multiple bit Error Correcting Architectures over Finite Fields” by Dr Mahesh Poolakkaparambil - a former member of the group.

Dr Abusaleh Jabir Oxford Brookes University From: September 2010
Until: December 2014

Design and Analysis of Memristor Based Reliable Crossbar Architectures

This project for the first time considered a detailed analysis of memristive crossbar arrays and formulated a closed form model of the so called “sneak-path” currents, endemic in these devices. The project also for the first-time modelled gas sensing abilities of the devices. The project culminated into a successful PhD project by Dr Adeyemo Adedotun, who is a former member of this group. The project also resulted in multiple granted patents.

Dr Abusaleh Jabir From: September 2014
Until: December 2018

Research impact

Intellectual property

The innovative research carried out by this group has generated the highest number of patentable IP within the University.

  • Patent No. GB1905392.5 embodies a highly innovative method of encoding, decoding and locking data into a single memristive device for applications in security and authentication. Patent No. GB1616837.9 embodies an innovative chemical sensor architecture for sensing and ‘memorising’ the sensed data, while Patent No. 10860291 embodies a novel memristive hybrid multifunction logic architecture that allows fabrications in 3D, while being applicable at higher frequencies than possible with traditional technologies. Other inventions include significantly improving reliability of chemical sensors by minimising the effects of process variability in a highly predictable manner (Patent No. GB1914221.5).
  • In fault and error tolerance in electronic hardware design, the group’s research has led to innovative error correction codes applied to error and attack mitigation in electronic hardware (Patent No. 20140229786, 9645886).
  • The research carried out by this group in synthesising and optimising logic circuits from its polynomial description led to an innovative graph-based technique, known as GfXpressTM, that can optimise circuits nearly two orders of magnitude better than industrial tools (Patent No. 9223917, 20110010141). 
Image of a microchip

Technical knowhow

3D graph of gas sensor performance
3D Graph of Memristive Gas Sensor Performance

The world class technical knowhow generated by this group is applied in various leading industries across the world by the group’s former members. These technical knowhow were developed by innovative research carried out by the group.

For example, Dr Adedotun Adeyemo, a former member of this group, after completing his PhD degree with Dr Jabir in the areas of memristive array architectures, now works with Infineon Technologies in Bristol UK as a Senior Verification Engineer, where the technical knowhow developed by the group is applied to developing a wide variety of industrial products. Dr Adeyemo has also been appointed by Oxford Brookes University as a member of Industrial Advisory Board and is also an industrial member and visiting fellow of this research group. 

Dr Mahesh Poolakkaparambil, another former member of this group, now holds the position of Head of Microcontroller Series Development Department with Continental Teves AG Automotive Industries in Frankfurt, Germany. The technical knowhow that Dr Poolakkaparambil gained from this group in Error Tolerance in Electronic Hardware is applied in reliable electronic braking systems in almost all vehicles worldwide.

Honours and awards

The group has won a number of prestigious best paper awards, for example at the:

  • IEEE IOLTS 2016 for the paper “Novel Memristive Logic Architectures”, Bremen, Germany
  • 9th IEEE International Congress on Ultra-Modern Telecom and Control Systems in Munich, Germany, 2017, for the paper "Learning Method for Ex-situ Training of Memristor Crossbar based Multi-Layer Neural Network." 

The group’s founder, Dr Abusaleh Jabir, is also the recipient of the much-coveted IEE/IET “Hartree Premium” best paper award for his paper “Minimization Algorithm for Three-Level Mixed AND-OR-EXOR/AND-OR-EXNOR Representation of Boolean Functions” published in the IET Proceedings, Part-E: Computers and Digital Techniques.

Best Research Paper Award certificate

Decision and policy making

Dr Saurabh Khandelwal at his desk
Dr Saurabh Khandelwal

The group members have served in National Stage decision making, for example, Dr Abusaleh Jabir recently served as a panellist for The Industrial Strategy Challenge Fund (ISCF) Digital Security by Design from the EPSRC-UK Research and Innovation (UKRI) funding.