Nabil Yassine
Senior Lecturer in Electric Vehicles
School of Engineering, Computing and Mathematics
Role
I am a Senior Lecturer in Electric Vehicles. I have been working at Oxford Brookes University since 2017. My previous work experience includes Research fellow in the future of Transport, Research Assistant, Lab Demonstrator and Associate Lecturer. I am an active member of the Electronics and Instrumentation Group and the High Voltage and Energy Storage Group. My background is in Biomedical Science and Electronic and Communication Engineering.
Teaching and supervision
Courses
- Automotive Engineering with Electric Vehicles (MSc)
- Electro-Mechanical Engineering BEng (BEng (Hons))
Modules taught
I am module leader for the following modules:
- Electrical Machines and Drives
- Electrical Power Systems
- Electric Vehicles
I also teach half of Electric Powertrain Systems
My teaching covers undergraduate year 2 modules and postgraduate modules. In addition, my teaching responsibilities include supervising students during their undergraduate and postgraduate projects.
Research
My research interests include Biomedical Engineering, Autonomous Vehicle Navigation Systems, Electric Powertrain control systems, Battery management systems, and Machine Learning (Adaptive Neural Networks). My current research projects include roadsign and lane marking recognition systems, bi-directional DC-DC converter control systems and Medical monitoring systems. My research involves integrating neural networks into systems for monitoring or detection purposes. This is a continuation of my PhD research which involved developing a neural network algorithm for detecting fatigue and distraction for drivers.
Groups
Publications
Journal articles
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Rajasekhar Nagulapalli1, Nabil Yassine1,*, Amr A. Tammam1, Steve Barker1 Khaled Hayatleh1, 'A 10.5 ppm/OC Modified Sub-1 V Bandgap in 28 nm CMOS Technology with only Two Operating Points'
Electronics [in press] (ISSN 2079-9292) (2024)
eISSN: 2079-9292AbstractPublished hereReference voltage/current generation is essential to the Analog circuit design. There have been several ways to generate quality reference voltage using Bandgap Reference (BGR). There are mainly 2 types: Current mode and Voltage mode. The current mode bandgap reference (CBGR) is widely accepted in the industry due to the output voltage that is below 1V. However, its drawbacks include a lack of proportional to absolute temperature (PTAT) current availability, large silicon area, multiple operating points, and large temperature coefficient (TC). In this paper, various operating points are explained in detail with diagrams. Similar to the conventional voltage mode bandgap reference (VBGR) circuits, modifications of the existing circuits with only two operating points have also been proposed. Moreover, the proposed BGR occupies a much smaller area due to eliminating the Complimentary to Absolute temperature (CTAT) current-generating resistor. A new self-biased opamp was introduced to operate from a 1.05V supply, reducing systematic offset and TC of the BGR. The proposed solution has been implemented in 28nm CMOS TSMC technology, and extraction simulations were performed to prove the robustness of the proposed circuit. The targeted mean BGR output is 500 mV, and across the industrial temperature range (-40 to 125°C), the simulated TC is approximately 10.5 ppm/°C. The integrated output noise within the observable frequency band is 19.6 µV (rms). A 200-point Monte Carlo simulation displays a histogram with a 2.6 mV accuracy of 1.2% (+/- 3-sigma). The proposed BGR circuit consumes 32.8 µW of power from a 1.05 V supply in a Fast process, Hot (125°C) corner. It occupies a silicon area of 81 x 42 µm (including capacitors). This design can aim for biomedical and sensor applications.
Keywords: Bandgap reference; Noise; Operating points; Self-bias; Offset phase-margin
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Nagulapalli R, Yassine N, Barker S, Georgiou P, Hayatleh K, 'A 261mV Bandgap reference based on Beta Multiplier with 64ppm'
International Journal of Electronics Letters 10 (4) (2021) pp.403-413
ISSN: 2168-1724 eISSN: 2168-1732AbstractPublished here Open Access on RADARIn this paper, a low voltage bandgap reference circuit has been proposed. The introduction of a modified beta multiplier bias circuit decreased the mismatch caused by the PMOS transistors opamp contribution. By shifting the fixed resistors to the NMOSs drain side, the beta multiplier bias was able to minimise threshold mismatch between the two NMOS transistors. A 200-point MC simulation showed 0.9mV standard deviation, with a 0.34% accuracy. The simulated temperature coefficient was 64ppm/0C. The proposed circuit consumed 5.04µW of power from a 0.45V power supply voltage. A prototype was implemented in 65nm CMOS technology occupying a 2888µm2 silicon area, with the nominal value of the reference at 261mV.
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R. Nagulapalli, K. Hayatleh, S. Barker, A. A. Tammam, F. J. Lidgey and N. Yassine, 'A High Sensitivity and Low Power Circuit for the Measurement of Abnormal Blood Cell Levels'
Journal of Circuits, Systems, and Computers 29 (4) (2019)
ISSN: 0218-1266 eISSN: 1793-6454AbstractPublished here Open Access on RADARThis paper describes a technique to detect blood cell levels based on the time-period modulation of a relaxation oscillator loaded with an Inter Digitated Capacitor (IDC). A digital readout circuit has been proposed to measure the time-period difference between the two oscillators loaded with samples of healthy and (potentially) unhealthy blood. A prototype circuit was designed in 65nm CMOS technology and post-layout simulations shows 15.25aF sensitivity. The total circuit occupies 2184µm2 silicon area and consumes 216µA from a 1V power supply.
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R. Nagulapalli, K. Hayatleh, S. Barker, B. Yassine, S. Zourob, S. Raparthy, N. Yassine, 'A Start-up Assisted Fully Differential Folded Cascode Opamp'
Journal of Circuits, Systems, and Computers 28 (10) (2018)
ISSN: 0218-1266 eISSN: 1793-6454AbstractPublished here Open Access on RADARThis paper explains the hidden positive feedback in the two-stage fully differential amplifier through external feedback resistors, and possible DC latch-up during the amplifier start-up. The biasing current selection among the cascode branches have been explained intuitively, With reference to previous literature. To avoid the latch-up problem irrespective of the transistor bias currents a novel, hysteresis based start-up circuit is proposed. An 87dB, 250MHz unity gain bandwidth amplifier has been developed in 65nm CMOS Technology and post-layout simulations demonstrate no start-up failures out of 1000 Monte-Carlo (6-Sigma) simulations. The circuit draws 126uA from a 1.2V supply and occupies the 2184um2 area.
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R. Nagulapalli, K. Hayatleh, S. Barker, A.A. Tammam, N. Yassine, B. Yassine, M. Ben-Esmael., 'A Low Noise Amplifier Suitable for Biomedical Recording Analog Front-End in 65nm CMOS Technology'
Journal of Circuits, Systems, and Computers 28 (8) (2018)
ISSN: 0218-1266 eISSN: 1793-6454AbstractThis paper presents a fully integrated Front-end, low noise amplifier, dedicated to the processing of various types of bio-medical signals, such as Electrocardiogram (ECG), Electroencephalography (EEG), Axon Action Potential (AAP). A novel noise reduction technique, for an operational transconductance amplifier (OTA), has been proposed. This adds a current steering branch parallel to the differential pair, with a view to reducing the noise contribution by the cascode current sources. Hence, this reduces the overall input referred noise of the Low Noise Amplifier (LNA), without adding any additional power. The proposed technique implemented in 65nm CMOS technology achieves 30dB closed loop voltage gain, 0.05Hz lower cut-off frequency and 100MHz 3-dB bandwidth. It operates at 1.2V power supply and draws 1µA static current. The prototype described in this paper occupies 3300µm2silicon area.Published here Open Access on RADAR -
K Hayatleh, S Zourob, R Nagulapalli,S Barker, N Yassine, P Georgiou*, F J Lidgey, 'A High Performance Skin Impedance Measurement Circuit for Biomedical Applications'
Journal of Circuits, Systems, and Computers 28 (7) (2018)
ISSN: 0218-1266 eISSN: 1793-6454AbstractThis paper describes a high-performance impedance measurement circuit for the application of skin impedance measurement in the early detection of skin cancer. A CMRR improvement technique has been adopted for OTAs to reduce the impact of high frequency common mode interference. A modified 3-OTA IA has been proposed to help with the impedance measurement. Such systems offer a quick, non-invasive and painless procedure, thus having considerable advantages over the currently used approach, which is based upon the testing of a biopsy sample. The sensor has been implemented in 65nm CMOS technology and post layout simulations confirms the theoretical claims we made and sensor exhibits sensitivity. Circuit consumes 45uW from 1.5V power supply. The circuit occupies 0.01954mm2 silicon area.Published here Open Access on RADAR -
R. Nagulapalli, K. Hayatleh, S. Barker, S. Zourob, N. Yassine, S. Raparthy and A. A. Tammam, 'A novel high CMRR Trans-Impedance Instrumentation Amplifier for biomedical applications'
Analog Integrated Circuits and Signal Processing 98 (2018) pp.233-241
ISSN: 0925-1030 eISSN: 1573-1979AbstractA compact high gain current mode instrumentation amplifier (IA) has been proposed for biomedical imaging applications. Conventional IAs rely on several matching resistors which occupies a lot of silicon area, the input and output common mode voltages are exactly same and the maximum applied signal amplitude is limited by internal node voltage swings. The present proposal eliminates the need for matching resistors by processing signals in the current mode. Hence input amplitudes are no longer limited by the voltage headroom and input and output common-mode voltages can be independent. An amplifier with a differential gain greater than 52dB and a common mode rejection ratio (CMRR) greater than 120dB has been implemented in 65nm CMOS Technology and Post layout simulations were presented. The total circuit occupies 4500um2 silicon area and circuit consumes ~260μA from 1.8V power supply.Published here Open Access on RADAR -
R Nagulapalli, K Hayatleh, S Barker, S Zourob, N Yassine, 'An OTA Gain Enhancement Technique for low power biomedical applications'
Analog Integrated Circuits and Signal Processing 95 (3) (2018) pp.387-394
ISSN: 0925-1030 eISSN: 1573-1979AbstractThe performance requirement of an operational trans-conductance amplifier (OTA) for the high gain and low power neural recording frontend has been addressed in this paper. A novel split differential pair technique is proposed to improve the gain of the OTA without any additional bias current requirements. The design demonstrates a significant performance enhancement when compared to existing techniques, such as gain-boosting and recycling. A qualitative and quantitative treatment is presented to explore the impact of the split ratio on the performance parameters of gain, bandwidth, and linearity. A prototype implemented in TSMC 65 nm CMOS technology achieved 68 dB open loop-gain (13 dB higher than the conventional circuit) and a 17 kHz 3-dB bandwidth. A linearity of − 62 dB has been achieved with 7 mV pk–pk signal at the input. The circuit operates from a 1 V supply and draws 0.6 uA static current. The prototype occupies 3300 um2 silicon area.Published here Open Access on RADAR -
S Zourob, K Hayatleh, S Barker, R Nagulapalli, N Yassine, R Ramsbottom and F J Lidgey, 'Increasing Signal to Noise Ratio and Minimizing Artefacts in Biomedical Instrumentation Systems'
Analog Integrated Circuits and Signal Processing 95 (3) (2018) pp.403-408
ISSN: 0925-1030 eISSN: 1573-1979AbstractCapturing a near-perfect, artefact free signal is an ideal of biomedicine. However, this depends on the removal of different types of artefact, all of which can be considered unwanted noise on the desired signal. Failure to remove artefacts could lead to a clinical misinterpretation of the results. All medical equipment such as electrocardiogram systems which use electrodes attached to patients suffer from artefacts, with effects ranging from minor blurring to significant distortion of the output signal(s). For this reason, it is important to identify how artefacts can influence the output signal. In this paper, we propose a new technique to detect and minimise movement artefacts using strain gauges embedded into the electrodes.Published here Open Access on RADAR -
N. Yassine, S. Barker, K. Hayatleh, B. Choubey, R. Nagulapalli, 'Simulation of Driver Fatigue Monitoring via Blink Rate Detection, using 65nm CMOS Technology'
Analog Integrated Circuits and Signal Processing 95 (3) (2018) pp.409-414
ISSN: 0925-1030 eISSN: 1573-1979AbstractThis paper proposes a system to detect and measure blink rate to determine fatigue levels. The method involved analysing specific frames to determine that a blink occurred, and then monitoring the time between successive blinks. The program was simulated in python using a Raspberry Pi Zero and a standard USB camera. For the blink rate detection block, a gate level schematic was implemented in Cadence software using 65nm CMOS technology. The design was based around an asynchronous 6-bit based edge counter which was designed using D-flip-flops. The simulation calculated the average blink rate and compared this to the most recent blink rate. The outcome would determine if an alarm signal should be sent to the alarm. The system consumed 130uA from a 1.2V power supply.Published here Open Access on RADAR -
Nagulapalli R, Hayatleh K, Barker S, Raparthy S, Yassine N, Lidgey FJ, 'A 0.6V MOS-only voltage reference for bio-medical applications with 40ppm/0c temperature drift'
Journal of Circuits, Systems, and Computers 27 (8) (2018)
ISSN: 0218-1266 eISSN: 1793-6454AbstractThis paper exploits the CMOS beta multiplier circuit to synthesize a temperature independentPublished here Open Access on RADAR
voltage reference suitable for low voltage and ultra-low power bio-medical applications. The
technique presented here uses only MOS transistors to generate PTAT and CTAT currents. A selfbiasing technique has been used to minimize the temperature and power supply dependency. A prototype in 65nm CMOS has been developed and occupies 0.0039mm, and at room temperature it generates a 204mV reference voltage with 1.3mV drift over a wide temperature range (from -40 to 1250C). This has been designed to operate with a power supply voltage down to 0.6V and consumes 1.8uA current from the supply. The simulated temperature coefficient is 40ppm/0C.
Conference papers
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Nagulapalli R, Hayatleh K, Yassine N, Barker S, 'A Novel Sub-1V Bandgap Reference with 17.1 ppm/0C Temperature coeficient in 28nm CMOS'
(2022)
ISSN: 0271-4302 eISSN: 2158-1525 ISBN: 9781665484862AbstractPublished here Open Access on RADARTraditional Banba bandgap is very popular in deep sub-micron CMOS technologies because of its sub 1V output nature. But unfortunately, it won’t provide PTAT nature current and has several operating points, unlike two in the voltage mode BGR. This work analyzes the Banba circuit in a detailed way so that it’s easy to demonstrate multiple stable operating and lists some of its other shortfalls. This paper presents a novel sub-1V bandgap architecture, which can provide PTAT current and sub-1V output without having multiple operating points. A modified self-bias opamp has been proposed to minimize the systematic offset and its temperature drift. A prototype was developed in 28nm TSMC CMOS technology and post-layout simulation results were performed. Proposed BGR targeted at 500mV works from 1V supply without having any degradation in the performance while keeping the integrated noise of 18.2µV and accuracy of 17.1ppm/0C, while the traditional Banba was resulting 23.4ppm/0C. Further, the circuit consumes 29.8µW of power and occupies 71*39µm2silicon area.
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R. Nagulapalli, K. Hayatleh, N. Yassine, S. Barker, R. Palani, 'A 0.82V Supply and 23.4 ppm/0C Current Mirror Assisted Bandgap Reference'
(2021)
ISSN: 2688-1454 ISBN: 9781665434294AbstractPublished here Open Access on RADARTraditional BGR circuits require a 1.05V supply due to the VBE of the BJT. Deep submicron CMOS technologies are limiting the supply voltage to less than 940mV. Hence there is a strong motivation to design them at lower supply voltages. The supply voltage limitation in conventional BGR is described qualitatively in this paper. Further, a current mirror-assisted technique has been proposed to enable BGR operational at
0.82V supply. A prototype was developed in 65nm TSMC CMOS technology and post-layout simulation results were performed. A self-bias opamp has been exploited to minimize the systematic offset. Proposed BGR targeted at 450mV works from 0.82-1.05V supply without having any degradation in the performance while keeping the integrated noise of 15.2μV and accuracy of 23.4ppm/0C. Further, the circuit consumes 21μW
of power and occupies 73*32μm2 silicon area. -
R. Nagulapalli, K. Hayatleh, S. Barker, S Zourob, N.Yassine & B Naresh Kumar Reddy, 'A Technique to Reduce the Capacitor size in Two Stage Miller compensated opamp'
(2018)
ISBN: 9781538644300AbstractPublished here Open Access on RADARIn this paper two stage Miller compensated opamp has been discussed qualitatively and quantitatively. A modification to the conventional compensation network has been proposed, which will reduce the capacitor size hence circuit area. Transfer function for the newly proposed solution has been derived and explained the results. A prototype was developed in 65nm TSMC CMOS technology and simulation results have been presented. Amplifier achieved 60dB low frequency gain, 12MHz bandwidth and 55° phase margin while consuming 650uW power from 1.2V power supply. Circuit occupies 5348um 2 silicon area.
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R. Nagulapalli, K. Hayatleh, S. Barker, S Zourob, N.Yassine & B N Kumar, 'High Performance Circuit Techniques for Neural Front-End design in 65nm CMOS'
(2018)
ISBN: 9781538644300AbstractPublished here Open Access on RADARIntegrated low noise neural amplifiers become recently practical in CMOS technologies. In this paper, a low
noise OTA technique has been proposed while keeping the power consumption constant. A capacitive feedback, ac coupled 46dB amplifier with high pass cutoff frequency close to the 90Hz has been achieved. The proposed amplifier has been implemented in 65nm CMOS technology; at room temperature circuit consumes 323uA current from 1.2V power supply. The circuit occupies 2627um2 silicon area. -
Nagulapalli R, Hayatleh K, Barker S, Zourob S, Yassine N, Venkatareddy A, 'A compact high gain opamp for Bio-medical applications in 45nm CMOS technology'
(2018) pp.231-235
ISBN: 9781509037749AbstractIn this paper a low opamp compensation technique suitable for the bio-medical application has been proposed and intuitive explained the existing compensation techniques. The Present technique relies on the passive damping factor control rather power hungry damping. Implemented in 45nm CMOS technology and simulated with Spectre. Simulation results shows that 100dB dc gain, well compensated 25MHz bandwidth opamp while driving a 1pF capacitive load. Draws with 12uW power consumption from 1V supply and occupying 0.004875mm2 silicon area.Published here Open Access on RADAR -
Nagulapalli R, Hayatleh K, Barker S, Zourob S, Yassine N, Sridevi S, 'A bio-medical compatible Self-bias opamp in 45nm CMOS technology'
(2017)
ISBN: 9781538617168AbstractIn this paper a low power, high gain self bias opamp suitable for biomedical applications has been described. A novel trans conductance boosting technique is introduced without having any additional power consumption. A simple technique of biasing the opamp has been introduced for very low offset and without having any requirement for external reference circuit. A prototype of two stage amplifier design presented to verify the proposed technique and described its robustness across PVT variations by showing simulation results. The design is implemented in 45nm CMOS technology and simulated with Spectre. Simulation results show that the proposed opamp exhibits FOM of 625 and 2 times better than state of art. The circuit consumes 26uW from 1.5V supply and occupying 0.00282mm2 silicon area.Published here -
Nagulapalli R, Hayatleh K, Barker S, Zourob S, Yassine N, Sridevi S, 'A microwatt low voltage bandgap reference for bio-medical applications'
(2017) pp.61-65
ISBN: 9781509067015AbstractIn this paper a microwatt low voltage bandgap reference suitable for the bio-medical application. The Present technique relies on the principle of generating CTAT and PTAT without using any (Bipolar Junction Transistor) BJT and adding them with a proper scaling factor for minimal temperature sensitive reference voltage. Beta multiplier reference circuit has been explored to generate CTAT and PTAT. Implemented in 45nm CMOS technology and simulated with Spectre. Simulation results shows that the proposed reference circuit exhibits 1.2% variation at nominal 745mV output voltage. The circuit consumes 16uW from 0.8V supply and occupying 0.004875mm2 silicon area.Published here Open Access on RADAR